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參數(shù)資料
| 型號(hào)： | LC7475 |
| 元件分類： | 畫面疊加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDIP22 |
| 封裝： | SDIP-22 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 150K |
| 代理商： | LC7475 |
LC7475
No.3885–5/12
Input Timing
Data and address words are input in serial format on SIN. A 16-bit address word is input after the falling edge of CS
followed by 16-bit data words. The address is incremented automatically after each data word. The data input timing is
shown in figure 1.
Only the lower eight bits of the address word are significant. Only the lower eight bits of data words at addresses 000H
to 0AFH, the lower 11 bits of data words at addresses 0B0H to 0BBH, and the lower 12 bits of data words at addresses
0BCH to 0BFH are significant. All non-significant bits should be set to 0.
RAM Memory Configuration
RAM memory is organized as 16-bit words as shown in table 1. Locations 000H to 0AFH are display RAM, locations
0B0H through to 0BBH are display line address registers, locations 0BCH to 0BDH are display control registers, location
0BEH is the video signal control register and location 0BFH is the general control register.
Table 1. Memory configuration
Note
× = don’t care
Figure 1. Input timing
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