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參數資料
| 型號： | LC74776 |
| 元件分類： | 畫面疊加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDIP30 |
| 封裝： | SDIP-30 |
| 文件頁數： | 17/35頁 |
| 文件大小： | 253K |
| 代理商： | LC74776 |
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No. 6018-24/35
LC74776, 74776M
DA 0 to 7
Register
Contents
Notes
State
Function
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
0
2
–
1
Extended command 6 identification code
1
–
1
0
–
0
First byte
COMMAND14 (VPS/PDC control setup command) I2C bus only
DA 0 to 7
Register
Contents
Notes
State
Function
7
–
0
Second byte identification bit
6
VMWSE2
0
V mask period start - From the retrace period
CPOUT pin (pin 13) V mask period switching 2
1
V mask period start - From 10H before the retrace period
5
VMWSEL
0
The V mask period is the retrace period
CPOUT pin (pin 13) V mask period switching
1
The V mask period is 9H
4
HBS2
0
Clock running discrimination 1 (2 times)
Clock running discrimination count setting
1
Clock running discrimination 2 (4 times)
3
HBS1
0
Framing code discrimination 1
Framing code discrimination selection
1
Framing code discrimination 2 (Single bad bits are ignored)
0
Error check valid (Error checking can be turned on or
2
BMS
off on a per-byte basis.)
1
Error check invalid (Applications can select whether data for
which an error is detected is held or writing on a per-byte basis.)
0
Data hold
1
EMS
1
Data write
(When the error bit is 0 in VPS mode.)
Error checking enabled for unused data bytes.
0
VPS: bytes 3, 4, and 6 to 10, PDC: bytes 7 to 12, header 1:
bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14
0
DCE
to 21, status 1 (3): bytes 7 to 25, status 2 (4): bytes 7 to 35
Error checking disabled for unused data bytes.
1
VPS: bytes 3, 4, and 6 to 10, PDC: bytes 7 to 12, header 1:
bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14
to 21, status 1 (3): bytes 7 to 25, status 2 (4): bytes 7 to 35
Second byte
Note: All registers are set to 0 when the LC74776/M is reset by the RST pin.
When set to 0, if there are no errors in bytes
for which error checking is turned on, those
bytes are written to P-S. When set to 1, all
bytes are written to P-S regardless of the error
status.
Specifies handling of bytes for which error
checking is set to off but in which an error
occurred when error checking is turned on
Error checking setting for unused data bytes.
Biphase (VPS), Hamming (PDC), and odd
parity (header)
相關PDF資料 |
PDF描述 |
|---|---|
| LC74776M | ON-SCREEN DISPLAY IC, PDSO30 |
| LC74776M | ON-SCREEN DISPLAY IC, PDSO30 |
| LC74780M | ON-SCREEN DISPLAY IC, PDSO24 |
| LC74780 | ON-SCREEN DISPLAY IC, PDIP24 |
| LC74781 | ON-SCREEN DISPLAY IC, PDIP24 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LC74776M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:On-Screen Display Controller IC |
| LC74776NM-9780-TRM | 制造商:SANYO Semiconductor Co Ltd 功能描述:ON-SCREEN DISPLAY IC, PDSO30 |
| LC74780 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:On-screen Video Display Controllers for VCRs |
| LC74780M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:On-screen Video Display Controllers for VCRs |
| LC74781 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:On-screen Video Display Controller for VCR Products |
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