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參數(shù)資料
| 型號： | LC74782M |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 畫面疊加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 183K |
| 代理商： | LC74782M |
} COMMAND5 (Display control setup command)
First byte
Second byte
Note: The register states are all set to zero when the LC74782/M is reset with the RST pin.
No. 4989-12/16
LC74782, 74782M
Register content
DA0 to DA7
Register name
State
Function
Note
7
—
0
Second byte identification bit
6
—
0
5
—
0
4
BCL
0
Background color present
Only valid with internal synchronization.
1
No background color (only the background level is set)
3
CB
0
Outputs a color burst signal.
Only valid when BCL is high.
1
Stops color burst signal output.
0
2
PH2
1
0
1
PH1
1
0
PH0
1
Sample background color phase
diagram for PAL mode color burst
*: When 2fsc NTSC is used
Phase 2
Phase 1
Phase 0
Background color (phase)
NTSC
PAL
0
π/2*
±
π/2
0
1
In phase*
In phase
0
1
0
3
π/2*
π/2
0
1
π*
±
π
1
0
3
π/4
±3
π/4
1
0
1
π/4
±
π/4
1
0
7
π/4
1
5
π/4
3
π/4
–
+
–
+
–
+
Register content
DA0 to DA7
Register name
State
Function
Note
7
—
1
6
—
1
Command 5 identification code
5
—
0
Display control
4
—
1
3
NP1
0
1
Switches between NTSC, PAL, PAL-M
2
NP0
0
and PAL-N
1
NON
0
Interlaced
Switches between interlaced and non-
1
Non-interlaced
interlaced displays
0
INT
0
External synchronization
Switches between external and internal
1
Internal synchronization
synchronization
NP1
NP0
0
1
0
NTSC
PAL-M
1
PAL
PAL-N
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