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參數資料
| 型號： | LC74981W |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | SQFP-208 |
| 文件頁數： | 5/12頁 |
| 文件大小： | 197K |
| 代理商： | LC74981W |
No. 6678-2/12
LC74981W
I/O Specifications
Input Signal Overview
Signal type
Pin No.
Pin
Description
Notes
6 to 13
YIN7 to 0
Y/Y/R
54 to 61
RIN7 to 0
Video signals
16 to 23
UIN7 to 0
C/Cb/G
64 to 71
GIN7 to 0
26 to 33
VIN7 to 0
–/Cr/B
74 to 81
BIN7 to 0
90
HITV
NTSC/PAL horizontal sync signal
91
VITV
NTSC/PAL vertical sync signal
Sync signals
92
HIDTV
DTV horizontal sync signal
93
VIDTV
DTV vertical sync signal
94
HIPC
PC horizontal sync signal
95
VIPC
PC vertical sync signal
96
BLKIH
Horizontal enable
Data enable signals
97
BLKIV
Vertical enable
36
CLKITV
NTSC/PAL clock
Pixel clocks
39
CLKIDTV
DTV clock
42
CLKIPC
PC video clock
167
XTAL
Display clock
NTSC, PAL, and DTV (480i and 480p) inputs
YCbCr signals conform to the CCIR 601 standard.
The YC C signal is a multiplexed CbCr signal.
PC input (up to XGA)
Three independent systems for both horizontal
and vertical sync signals
Any input polarity may be used. The LC74981W
discriminates internally.
Positive logic (active-high) input
A composite signal can be input to BLKIH.
(BLKIV must be tied high in this case.)
Three independent input systems
Fixed frequency crystal oscillator (65 MHz maximum)
Output Signal Overview
Signal type
Pin No.
Pin
Description
Notes
106 to 111
ROEVEN5 to 0
Even pixels, red
114 to 119
GOEVEN5 to 0
Even pixels, green
Video signals
122 to 127
BOEVEN5 to 0
Even pixels, blue
130 to 135
ROODD5 to 0
Odd pixels, red
138 to 143
GOODD5 to 0
Odd pixels, green
146 to 151
BOODD5 to 0
Odd pixels, blue
Sync signals
162
HOUT
Horizontal sync signal
163
VOUT
Vertical sync signal
Data enable signals
102
BLKHOUT
Horizontal enable
103
BLKVOUT
Vertical enable
154
DCLK1
Single-phase clock
Pixel clocks
155
DCLK1B
Single-phase clock (inverted)
158
DCLK2
Two-phase clock
159
DCLK2B
Two-phase clock (inverted)
For each RGB signal: 6 bits and 2 phases
Also provides single-phase output (In this mode
the odd pixel pins are used for output.)
The sync period, position, and polarity can be set.
A composite sync signal can be output from VOUT.
Outputs the same frequency as that of the crystal
oscillator.
The enable period and the polarity can be set.
A composite signal can be output from BLKVOUT.
Outputs a frequency 1/2 that of the crystal
oscillator.
Control Signal Overview
Signal type
Pin No.
Pin
Description
Notes
172
AICS
Chip select
Three-wire bus
173
AIDA
Data bus
174
AICK
Bus clock
175
SDA
Data bus
I2C-bus
176
SCL
Bus clock
Used for OSD control and γ correction
characteristics settings.
Used to set the internal control registers and to
output internal status information.
The slave address is “0111000+ (R/W)”.
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