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參數資料
| 型號： | LC74986NW-XXXXF |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 封裝： | SQFP-144 |
| 文件頁數： | 10/15頁 |
| 文件大小： | 78K |
| 代理商： | LC74986NW-XXXXF |
No.7713-4/15
LC74986NW-XXXXF, 74986NW-XXXXV
Continued from preceding page.
Signal type
Number of pins
Symbol
Description
Notes
Max85MHz("-XXXXF"),
Max40MHz("-XXXXV")
Pixel clock
Clock enable
1
CLKI
Port A system clock
Max85MHz("-XXXXF"),
Max40MHz("-XXXXV")
1
DCLKI
Display clock
Max85MHz("-XXXXF"),
Max40MHz("-XXXXV")
1
VPBCK
Port B system clock
Positive logic
1
CLKIEN
Port A system clock enable
Fixed oscillator
Max85MHz("-XXXXF"),
Max40MHz("-XXXXV")
1
XTAL
Used for the control bus and
various detection functions
System reset
Inverted logic
1
RST
System reset
External video
Inputs a video signal synchronized with the output
Dither processing possible. Image quality
adjustments not possible.
6-bit input also possible
Positive logic
8
VPB1
8
VPB2
8
VPB3
1
VPBEN
(VPBDEN)
External video signal
(input port B, dual output)
External video signal enable
(port B system composite data
enable)
Output Signals
Signal type
Number of pins
Symbol
Description
Notes
Dithered 6-bit output also possible
Dual output also possible. (Odd/even inversion possible)
First data
Dedicated dual system output. (Odd/even inversion
possible)
Second data
The sync signal, position, and polarity can be set.
The polarity can be set.
Video signals
Sync signals
Data enable signals
Pixel clocks
Clamp pulse
8
ROUT
R
8
GOUT
G
8
BOUT
B
8
ROUT_2 (VPB1)
8
GOUT_2 (VPB2)
8
BOUT_2 (VPB3)
1
HSO
VSO
DEHO
DEVO
Dual output
(input port B, external video
signal)
Horizontal sync signal
Vertical sync signal, composite signal
Horizontal data enable
Vertical data enable, composite enable
The polarity can be inverted.
1
CLKIO
Outputs the input clock
The polarity can be inverted. Divided-by-two output
possible in dual output mode.
1
DCLKO
Display clock
Output at the clamp position. The position can be
changed. The pulse width can be changed.
1
CLPP
Used for A/D conversion
Clamp levels
Divided output
signal for external
PLL circuit
Clamp level discrimination output
(Too large: low, too small: high, match: high
impedance)
1
CLPVPA1
VP1 clamp level
1
CLPVPA2
VP2 clamp level
1
CLPVPA3
VP3 clamp level
1
PLLHIO
For an external PLL circuit
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