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參數(shù)資料
| 型號： | LC78625E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 2/35頁 |
| 文件大小： | 535K |
| 代理商： | LC78625E |
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CD System Block Diagrams
Pin Applications
1. HF signal input circuit; Pin 11: EFMIN, pin 10: EFMO, pin 9: EFMO, pin 1: DEFI, pin 13: CLV+
An EFM signal (NRZ) sliced at an optimal level can be
acquired by inputting the HF signal to EFMIN.
The LC78625E handles defects as follows. When a high
level is input to the DEFI pin (pin 1), the EFMO (pin 9) and
EFMO (pin 10) pins (the slice level control outputs) go to the
high-impedance state, and the slice level is held. However,
note that this function is only valid in CLV phase control
mode, that is, when the V/P pin (pin 15) is low. This function
can be used in combination with the LA9230/40 series DEF
pin.
Note: If the EFMIN and CLV+ signal lines are too close to
each other, unwanted adiation can result in error rate
degradation. We recommend laying a ground or VDD
shield line between these two lines.
2. PLL clock generation circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK
Since the LC78625E includes a VCO circuit, a PLL circuit
can be formed by connecting an external RC circuit. ISET is
the charge pump reference current, PDO is the VCO circuit
loop filter, and FR is a resistor that determines the VCO
frequency range.
(Reference values)
R1 = 68 k
, C1 = 0.1 F
R2 = 680 k
, C2 = 0.1 F
R3 = 1.2 k
Note: We recommend using a ±5.0% tolerance carbon film
resistor for R3.
No. 5502-10/35
LC78625E
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