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參數資料
| 型號： | LC78637E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, QFP-80 |
| 文件頁數： | 2/20頁 |
| 文件大小： | 188K |
| 代理商： | LC78637E |
LC78637E
-10-
Pin Function Table
Pin
No.
Pin Name
I/O
State after
Reset
Function
1
LPF
AO
—
RF signal DC level detection LPF capacitor connection pin
2
AIN
AI
—
A signal input pin
3
CIN
AI
—
C signal input pin
4
BIN
AI
—
B signal input pin
5
DIN
AI
—
D signal input pin
6
AVSS1
—
Analog ground pin 1. Must be connected to 0V.
7
AVDD1
—
Analog power supply pin 1
8
FEC
AO
—
FE signal LPF capacitor connection pin
9
RFMON
AO
ZHI
IC internal analog signal monitor pin
10
VREF
AO
RFVDD /2 VREF voltage output pin
11
JITTC
AI
—
Jitter detection capacitor connection pin
12
EIN
AI
—
E signal input pin
13
FIN
AI
—
F signal input pin
14
TEC
AO
—
TE signal LPF capacitor connection pin
15
TE
AO
—
TE signal output pin
16
TEIN
AI
—
TES signal generation TE signal input pin
17
AVSS2
—
Analog ground pin 2. Must be connected to 0V.
18
AVDD2
—
Analog power supply pin 2
19
LDD
AO
ADAVDD Laser power control signal output pin
20
LDS
AI
—
Laser power detection signal input pin
21
FDO
AO
ADAVDD /2 Focus control signal output pin. D/A output
22
TDO
AO
ADAVDD /2 Tracking control signal output pin. D/A output
23
SLDO
AO
ADAVDD /2 Thread control signal output pin. D/A output
24
SPDO
AO
ADAVDD /2 Spindle control signal output pin. D/A output
25
CONT4
I/O
Input
General-purpose I/O pin 4
26
CONT5
I/O
Input
General-purpose I/O pin 5
27
SBCK/
CONT6
I/O
Input
General-purpose I/O pin 6, or subcode
read clock input pin
Controlled by command from
microcomputer. When not used, set
as input pin and connect to 0V or
set as output pin and leave open.
28
SBCK/FG
I
—
Subcode read clock input pin / FG signal input pin / external emphasis
setting pin
Set pin function with a command. When not used, connect to 0V.
29
DEFECT
O
L
Defect pin
30
V/
P
OH
Rough servo/phase control automatic switching monitor output pin. “H”:
Rough servo, “L”: Phase servo
31
FSEQ
O
L
Detected synchronization signal output pin
“H” when synchronization signal detected from EFM signal and internally
generated synchronization signal match.
32
MONI1
O
L
Internal signal monitor pin 1
33
MONI2
O
L
Internal signal monitor pin 2
34
MONI3
O
L
Internal signal monitor pin 3
35
MONI4
O
L
Internal signal monitor pin 4
36
MONI5
O
L
Internal signal monitor pin 5
37
VSS
—
Digital ground pin. Must be connected to 0V.
38
VDD
—
Digital power supply pin
39
DOUT
O
Digital OUT output pin. EIAJ format
40
TEST
I
Test input pin. Must be connected to 0V.
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