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參數資料
| 型號： | LC78681E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數： | 7/23頁 |
| 文件大小： | 241K |
| 代理商： | LC78681E |
Notes: 1. The fall of RWC when the desired number of tracks is input in binary format starts the track count.
2. During track counting, TOFF is high and the tracking servocontroller is turned off. For this reason, issuance
of a feed motor signal is required.
3. The Track Count In and Track Count Out commands cause the WRQ signal to change from the Q subcode
standby monitor when normal to the track count monitor. WRQ goes high at half the track count and low
again at the end of the count. The microprocessor monitors WRQ to detect track count completion.
4. When a 2-byte Command Reset command is not issued, the track count starts again. For example, to advance
20,000 tracks, the microprocessor can set the track count number to 200 and wait 100 WRQ pulses.
5. The Brake command is used to bring the pickup to the track when counting is finished.
Error Flag Output (pin 45: EFLG and pin 49: FSX)
The 7.35 kHz FSX frame synchronization signal is divided down from the reference clock. The status of error correction
in each frame is output on EFLG, as shown in the figure, where the number of high pulses in each FSX period indicates
the quality of the replay signal.
P, Q, and R through W Subcode Output Circuit (pin 46: PW, pin 44: SBSY, pin 47: SFSY and pin 48: SBCK)
PW is the subcode signal output pin. The falling edge of SFSY starts the 136 s period during which SBCK is clocked
eight times, allowing all codes — P, Q, and R through W — to be read. The signals appearing at the PW pin change with
the rising edge of SBCK. When SBCK is static, the P code is input to PW. SFSY is the signal output for each subcode
frame, and the rising edge of this signal indicates standby status for output of the subcode symbols (P through W).
Subcode data P if output simultaneously with the falling edge of this signal.
SBSY is output for each subcode block. It is high during the S0 and S1 synchronization cycles. Its falling edge indicates
the end of synchronization and the start of EIAJ-format data within the subcode block.
No. 4521-15/23
LC78681E
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