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參數資料
| 型號： | LC7872E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數： | 17/17頁 |
| 文件大小： | 295K |
| 代理商： | LC7872E |
Pin Functions
No. 4868-9/17
LC7872E
Pin No.
Symbol
I/O
Function
1S1
I
S1
S2
CD DSP
CD DSP selection
00
LC7861N/67
2S2
I
10
LC7860K/63
11
LC7868/69/681
3
SBCK
O
Subcode R to W readout clock
4
SFSY
I
Subcode frame synchronization signal
5PWI
Subcode R to W data
6
SBSY
I
Subcode block synchronization signal
7VDD1—
Digital system power supply
8CEI
Serial input or control pin during serial output
9DOO
Serial data output (N-ch open drain)
10
DI
I
Serial data input
11
CL
I
Serial data I/O clock
12
MUTE
I
Control signal that invalidates the subcode data
13
VSS1—
Digital system ground
14
WE
O
DRAM control
15
RAS
O
DRAM control
16
A0
O
DRAM address
17
A1
O
DRAM address
18
A2
O
DRAM address
19
A3
O
DRAM address
20
A4
O
DRAM address
21
A5
O
DRAM address
22
A6
O
DRAM address
23
A7
O
DRAM address
24
DB0
I/O
DRAM data
25
CAS
O
DRAM control
26
DB1
I/O
DRAM data
27
OE
O
DRAM control
28
DB2
I/O
DRAM data
29
DB3
I/O
DRAM data
30
CB
I
High: color bar output
(pull-down resistor built in)
Low: normal mode
31
CDGM
O
Outputs a high level when a CD-G disk detected
32
TRANS0
O
Transparency digital output
33
TRANS1
O
Transparency digital output
34
TRANS2
O
Transparency digital output
35
TRANS3
O
Transparency digital output
36
TRANS4
O
Transparency digital output
37
TRANS5
O
Transparency digital output
38
VSS2—
Composite video D/A converter ground
39
VDD2—
Composite video D/A converter power supply
40
BIAS
O
Ripple exclusion capacitor connection
41
VIDEO
O
Composite video output (8-bit D/A converter output)
42
TEST
I
Test pin. Must be tied low in normal operation (pull-down resistor built in)
43
LINE
I
When pin NP2 is high: High: 263H, Low: 262H
When pin NP2 is low: High: 312H, Low: 314H
44
FSCIN
I
Subcarrier clock input (feedback resistor built in)
45
VSYNC
O
Vertical synchronization signal output
46
TEST1
I
Test pin. Must be tied low in normal operation (pull-down resistor built in)
47
YS
O
Superimposition control output
48
CSYNC
O
Composite synchronization signal output
49
4FSC2
I
Superimposition mode external clock input (feedback resistor built in)
50
EFLG
O
Error state monitor
Continued on next page.
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