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參數(shù)資料
| 型號： | LC83026E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 275K |
| 代理商： | LC83026E |
No. 5663-4/16
LC83026E
Continued from preceding page.
Pin
Pin No.
I/O
Function
DVDD1 to 3 17, 18, 72
—
Digital block VDD (Must be connected to +5 V.)
<Make connections as short as possible so that no potential differences occur between any of the VDD pins.>
DVSS1 to 3 21, 48, 73
—
Digital block VSS (Must be connected to ground.)
<Make connections as short as possible so that no potential differences occur between any of the VSS pins.>
ADLVDD
35
—
A/D converter VDD (left channel) (Connect to +5 V.)
ADRVDD
41
—
A/D converter VDD (right channel) (Connect to +5 V.)
ADMVDD
46
—
A/D converter VDD (microphone) (Connect to +5 V.)
DALVDD
24
—
D/A converter VDD (left channel) (Connect to +5 V.)
DARVDD
31
—
D/A converter VDD (right channel) (Connect to +5 V.)
ADLVSS
33
—
A/D converter VSS (left channel) (Connect to ground.)
ADRVSS
39
—
A/D converter VSS (right channel) (Connect to ground.)
ADMVSS
44
—
A/D converter VSS (microphone) (Connect to ground.)
DALVSS
27
—
D/A converter VSS (left channel) (Connect to ground.)
DARVSS
28
—
D/A converter VSS (right channel) (Connect to ground.)
Power
supply
Design the wiring so that potential differences do
not occur between the analog system VDD pins and
either other analog system VDD pins or the digital
system VDD pins.
Design the wiring so that potential differences do
not occur between the analog system VSS pins and
either other analog system VSS pins or the digital
system VSS pins.
Pin Circuits
Pins
Specifications
Circuit
ASO, LRCKO, BCKO, RAS, CAS,
DREAD, DWRT, FS384O, A0 to A8
TTL output
ADL2, ADL3, ADM2, ADM3, ADR2,
ADR3
Analog output
Schmitt input
DALP, DALN, DARP, DARN
SI, SICK, SIRQ, SRDY, (OSC1)
Low Schmitt input
FS384I, BCKI, ASI, LRCKI
Normal input
TEST1 to TEST5
Input with built-in pull-up resistor
RES
Input with built-in pull-down resistor
SELC, SAIF, SAOF
P3, P4, SIAK
CMOS intermediate current output
Continued on next page.
Output data
Input data
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