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參數資料
| 型號： | LC83200W |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數： | 10/11頁 |
| 文件大小： | 466K |
| 代理商： | LC83200W |
LC83200W
No.7902-8/11
Control Registers
Table 1 Register Map
D15
D14
D13
D12
D11
D10
D9
D8
D7
CE
PRG4
PRG3
PRG2
PRG1
PRG0
FM2
FM1
FM0
Must be“0”
External Configuration Mode1
(Table 2)
External Configuration Mode2
(Table 3)
D6
D5
D4
D3
D2
D1
D0
MUTE
STEREO
PLL STOP
PLL1
PLL0
“0”:mute off
“0”: bypass off
“0”: stop on
“1”:mute on
“1”: bypass on
“1”: stop off
External Configuration Mode3 (Table 4)
Reserve (Not use)
Table 2 External Configuration Mode 1 DH Mode Coefficient Configuration Register
PRG4
PRG3
PRG2
PRG1
PRG0
Mode
0
Stereo Mix-down
0
1
48kHz room1
0
1
0
48kHz room2
0
1
48kHz room3
Reserved (Not use)
1
0
Stereo Mix-down
1
0
1
44.1kHz room1
1
0
1
0
44.1kHz room2
1
0
1
44.1kHz room3
Reserved (Not use)
Table 3 External Configuration Mode 2 Audio Interface Configuration Register
FM2
FM1
FM0
Audio Data Format
0
24bits Right-Justified
0
1
20bits Right-Justified
0
1
0
18bits Right-Justified
0
1
16bits Right-Justified
1
0
24bits IIS
1
0
1
24bits Left-Justified
Reserved (Not use)
Note: Supports 32fs, and 48 to 64fs audio bit clock frequencies.
Table 4 External Configuration Mode 3 Operating Clock Configuration Register
PLL1
PLL0
PLL SW
Example1. 48kHz
Example2.
0
2 times
48kHz
×512fs×2 = 49.152MHz
27MHz
×2 = 54MHz
0
1
4 times
48kHz
×256fs×4 = 49.152MHz
13.5MHz
×4 = 54MHz
1
0
Reserve
Not use
1
Reserve
Not use
Note: The operating clock of the LC83200W has a frequency of approximately 50MHz. Due to this setting, an
operating clock with a frequency of approximately 50MHz is generated by doubling or quadrupling the clock
frequency, which has been input to the PLL circuit inside the IC chip.
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