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參數(shù)資料
| 型號： | LC83210W |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 471K |
| 代理商： | LC83210W |
LC83210W
No.7974-5/11
Pin Functions
Block
Pin No.
Pin Name
I/O
Description
7
LRCLOCK
I
Audio data input LR clock
8
SCLOCK
I
Audio data input bit clock
3
SDI0
I
Audio data serial input (L, R)
4
SDI1
I
Audio data serial input (Ls, Rs)
Audio IN
5
SDI2
I
Audio data serial input (C, LFE)
Audio OUT
2
SDO
O
Audio data serial output (L, R)
41
ENABLE
I
Command enable input
40
CLOCK
I
Serial data input clock
Host I/F
39
DATA
I
Address and data input
Reset
47
RESET
I
System reset input (Low: reset on)
14
R
I
VCO bias resistor pin
15
VCNT
I
VCO control input pin
23
MCLOCK
I
Operating clock input pin
PLL
16
PDO
O
VCO charge pump output pin
1, 19
VDD1
-
I/O power supply
25, 37, 43
VDD2
-
Digital power supply
13
AVDD
-
Dedicated power supply for PLL
6, 20
VSS1
-
I/O ground
31, 36, 46
VSS2
-
Digital ground
Power supply
12
AVSS
-
Dedicated ground for PLL
9, 10, 11, 17, 24
I
Test pins
Test
32, 38
O
Test pins
42
CMODE
I
Parallel (high)/Serial (low) select pin
30
PRG4
I
29
PRG3
I
28
PRG2
I
27
PRG1
I
26
PRG0
I
Dolby headphone/Dolby Virtual Speaker mode select pin
35
FMT2
I
34
FMT1
I
33
FMT0
I
Audio I/O select pin
44
MUTE
I
Mute pin (High: mute on)
45
STEREO
I
L/R signal bypass pin (High: stereo bypassed)
18
PLL STOP
I
Power save pin (Low: PLL circuit turned off)
21
PLL1
I
Parallel control port
22
PLL0
I
PLL clock select pin
* COMDE: The setting of the control register can be changed as follows by switching this pin high or low.
Low: Serial setting via the microcontroller interface
High: Parallel setting using IC pins
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