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參數(shù)資料
| 型號(hào)： | LC89962 |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP8 |
| 封裝： | DIP-8 |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大小： | 117K |
| 代理商： | LC89962 |
Allowable Operating Ranges at Ta = 25°C
Note 1. The input signal must be input with low impedance for correct operation of sync-tip clamping.
Electrical Characteristics at Ta = 25°C, VDD = 5.0 V, CLK = 3.579545 MHz; 300 mV p-p
Test Conditions
1. The supply current with no input signal
2. The following formula is used to calculate the voltage gain (GV).
VOUT [mVp-p]
GV = 20log ——————— [dB]
500 [mVp-p]
3. The following formula is used to calculate the frequency characteristics (Gf).
V2 [mVp-p]
Gf = 20log —————— [dB]
V1 [mVp-p]
During this test, adjust Vbias so that the input signal DC level is 250 mV higher than the clamp level.
No. 5420-2/6
LC89962, LC89962M
Parameter
Symbol
Switch states
min
typ
max
Unit
SW1
SW2
SW3
Test conditions
Supply current
IDD
aaa
*1
5
15
25
mA
Voltage gain
GV
aba
*2
–2
0
+2
dB
Frequency characteristics
Gf
bba
*3
–2
–10
dB
Differential gain
DG
a
*40
5
%
Differential phase
DP
a
*4
0
5
deg
Linearity
LS
a
*537
40
43
%
Clock leakage
Lck
a
b
a
*6
5
50
mVrms
Noise
NO
aba
*7
1
2
mVrms
Output impedance
ZO
ab
a
b
*8
220
370
520
Delay time
TD
a
b
a
*9
63.33
s
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply voltage
VDD
4.75
5.0
5.25
V
Clock input amplitude
VCLK
Sine wave
200
300
500
mVp–p
Clock frequency
FCLK
3.579545
MHz
Signal input amplitude
VIN
(*1)
500
572
mVp–p
Output signal symbol
Input signal
VOUT
Sine wave: 200 kHz, 500 mV p-p
Output signal symbol
Input signal
V1
Sine wave: 200 kHz, 200 mV p-p
V2
Sine wave: 3.58 MHz, 200 mV p-p
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