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參數(shù)資料
| 型號： | LD3986J33R-E |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | DUAL ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE REG. FOR USE WITH VERY LOW ESR OUT. CAPACITORS |
| 中文描述： | 雙超低壓降低噪聲BICMOS工藝電壓退訂。至于一些使用低ESR輸出。電容器 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 230K |
| 代理商： | LD3986J33R-E |
1/12
September 2005
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INPUT VOLTAGE FROM 2.5V TO 6V
STABLE WITH LOW ESR CERAMIC
CAPACITORS
ULTRA LOW DROPOUT VOLTAGE (60mV
TYP. AT 150mA LOAD, 0.4mV TYP. AT 1mA
LOAD)
VERY LOW QUIESCENT CURRENT (155μA
TYP. AT NO LOAD, 290μA TYP. AT 150mA
LOAD; MAX 2μA IN OFF MODE)
GUARANTEED OUTPUT CURRENT UP TO
150mA FOR BOTH OUTPUTS
DUAL OUTPUT VOLTAGES
FAST TURN-ON TIME: TYP. 120μs (C
O
=1μF,
C
BYP
=10nF AND I
O
=1mA)
LOGIC-CONTROLLED ELECTRONIC
SHUTDOWN
INTERNAL CURRENT AND THERMAL LIMIT
OUTPUT LOW NOISE VOLTAGE 30μV
RMS
OVER 10Hz to 100KHz
S.V.R. OF 50dB AT 1KHz, 40dB AT 10KHz
TEMPERATURE RANGE: -40°C TO 125°C
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DESCRIPTION
The LD3986 provides up to 150mA at each output,
from 2.5V to 6V input voltage. The ultra low
drop-voltage, low quiescent current and low noise
make it suitable for low power applications and in
battery powered systems. Regulator ground
current increases only slightly in dropout, further
prolonging the battery life. Power supply rejection
is 50 dB at 1KHz and 40 dB at 10KHz. High power
supply rejection is maintained down to low input
voltage levels common to battery operated
circuits. Shutdown Logic Control function is
available for each output, this means that when
the device is used as local regulator, it is possible
to put a part of the board in standby, decreasing
the total power consumption. The LD3986 is
designed to work with low ESR ceramic
capacitors. Typical applications are in mobile
phone and similar battery powered wireless
systems.
LD3986
SERIES
DUAL ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE
REG. FOR USE WITH VERY LOW ESR OUT. CAPACITORS
Figure 1: Schematic Diagram
Flip-Chip
Rev. 3
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