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參數(shù)資料
| 型號： | LE57D111TC |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大小： | 546K |
| 代理商： | LE57D111TC |
P R E L I M I N A R Y
Le57D11 Data Sheet
3
PRODUCT DESCRIPTION
The Le57D11 device is designed for long loop high-density POTS applications requiring a power saving, small footprint SLIC.
The Le57D11 device increases line card density by integrating two SLIC devices into a single 32 pin package. This reduction in
board space allows for higher density linecard, which allows for amortizing common hardware across more channels. The
Le57D11 device gives line card designers a simple control interface that supports four states: Active, Polarity Reversal, Standby,
and Disconnect (Ringing). The Le57D11 device is low cost and high performance, providing key features required for POTS
markets requiring only loop start. The device includes a thermal management resistor option.
BLOCK DESCRIPTIONS
Fault Detector
These blocks provide fault detection on a per channel basis for short to ground, short to battery, or certain AC faults. The Le57D11
device provides fault detection by having one fault detector in each channel. Under fault conditions — either a short to ground,
a short to battery, or specified AC power cross faults — the Le57D11 device detects the longitudinal unbalance and trips the
detector. Once the detector is tripped, the CFLT pin is pulled low and keeps toggling between Vth1 and Vth2 (refer Figure 2) until
the fault is removed. An external 0.1μF capacitor is connected between the CFLT pin and AGND, which provides a fault trigger
delay of about 4 mS (T1) and release delay of 24 mS (T2). During release delay, the affected channel is shutdown which sets Tip
and Ring to a Disconnect state. The trigger delay prevents short transients on Tip and Ring from triggering the channel shutdown
when a fault is not present.
Figure 1.
Fault Detector
Figure 2.
Fault Detection Waveform
Bias
Shutdown
Control
Bias
Block
Fault
Release
CFLT
TIP
V
long
RING
V
lb
Fault Detector
C
FLT
Release
T
2
T
1
T
2
T
1
Release
V
CFLT
Time
Fault
Trigger
Fault
Trigger
5V
V
th1
V
th2
T1
CFLT Vth1
Vth2
–
(
)
Itrigger
=
T2
Irelease
Vth2
–
)
CFLT Vth1
=
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