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參數資料
| 型號： | LG1600FXH |
| 廠商： | Lineage Power |
| 英文描述： | Clock and Data Regenerator(時鐘數據再生器) |
| 中文描述： | 時鐘和數據再生（時鐘數據再生器） |
| 文件頁數： | 10/20頁 |
| 文件大小： | 492K |
| 代理商： | LG1600FXH |
Data Sheet
August 1999
LG1600FXH Clock and Data Regenerator
10
Lucent Technologies Inc.
Test Circuit
12-3234(F)r.6
Notes:
Resistor R
X
determines the PLL bandwidth and is required for normal operation. The LG1600FXH differs in this respect from the LG1600AXD
CDR, which has an internal resistor that sets a minimum bandwidth. The recommended value is 140
for optimal jitter transfer performance.
Capacitor C
X
is optional and can be used to increase the damping of the PLL in critical applications.
The outputs may be either ac coupled, as indicated, or dc terminated into 50
. In the first case, good output return loss can be obtained. The
latter configuration provides a 0 mV to –800 mV output swing for easy interface to dc-coupled circuits.
Figure 10. LG1600FXH Typical Test Circuit
500 k
+
VCO
Q
D
V
+
CLKO
V
–
CLKO
31
26
D
FREQ. &
PHASE
DETECT.
0°
90°
LOOP CONTROL &
SIGNAL DETECT
0.047
μ
F
11
14
9
7
V
REF
C
EXT
R
EXT
LOS
V
–TH
51
V
–FB
48
55
60
65
V
–IN
V
+IN
V
+FB
0.047
μ
F
0.047
μ
F
0.047
μ
F
1 k
50
25 k
50
25 k
1 k
43
38
V
+OUT
V
–OUT
35
0.047
μ
F
50
50
DATA
GENERATOR
OPTIONAL
THRESHOLD
CONTROL
ALTERNATIVE
50
50
OPTIONAL
C
a
> 0.1
μ
F/f
B
V
SS
5.2 V
+
OPTIONAL
C
b
> 100 pF/f
B
50
50
C
X
OPTIONAL
(SEE TEXT)
R
X
= 140
REQUIRED
0.047
μ
F
10 k
V
DD
5 V
+
V
LOS
V
SS
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