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參數(shù)資料
| 型號(hào)： | LM1971MWC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, UUC |
| 封裝： | WAFER |
| 文件頁(yè)數(shù)： | 10/13頁(yè) |
| 文件大小： | 290K |
| 代理商： | LM1971MWC |
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Application Information
SERIAL DATA FORMAT
The LM1971 uses a 3-wire serial communication format that
is easily controlled by a microcontroller. The timing for the
3-wire set, comprised of DATA, CLOCK, and LOAD is shown
in
Figure 2. As depicted in Figure 2, the LOAD line is to go
low at least 150 ns before the rising edge of the first clock
pulse and is to remain low throughout the transmission of the
16 data bits. The serial data is composed of an 8-bit address,
which must always be set to 0000 0000 to select the single
audio channel, and 8 bits for attenuation setting. For both ad-
dress data and attenuation setting data, the MSB is sent first
with the address data preceding the attenuation data. Please
refer to
Figure 3 to confirm the serial data format transfer
process.
Table 1 shows the various Address and Data byte values for
different attenuation settings. Note that Address bytes other
than 0000 0000 are ignored.
POT SYSTEM ARCHITECTURE
The Pot’s digital interface is essentially a shift register
where serial data is shifted in, latched, and then decoded.
Once new data is shifted in, the LOAD line goes high, latch-
ing in the new data. The data is then decoded and the appro-
priate switch is activated to set the desired attenuation level.
This process is continued each and every time an attenua-
tion change is made. When the Pot is powered up, it is
placed into the Mute mode.
POT DIGITAL COMPATIBILITY
The Pot’s digital interface section is compatible with TTL or
CMOS logic. The shift register inputs act upon a threshold of
two diode drops above the ground level (Pin 3) or approxi-
mately 1.4V.
TABLE 1. Attenuator Register Set Description
Address Register (Byte 0)
MSB LSB
A7–A0
0000 0000
Channel 1
0000 0001
Ignored
0000 0010
Ignored
Data Register (Byte 1)
Contents
Attenuation (dB)
MSB LSB
D7–D0
0000 0000
0.0
0000 0001
1.0
0000 0010
2.0
0000 0011
3.0
:::::
::
0001 0000
16.0
0001 0001
17.0
0001 0010
18.0
0001 0011
19.0
:::::
::
0011 1101
61.0
0011 1110
62.0
0011 1111
96 (Mute)
0100 0000
96 (Mute)
:::::
::
1111 1110
96 (Mute)
1111 1111
96 (Mute)
DS012353-3
*Note: Load and clock falling edges can be coincident, however, the clock falling edge cannot be delayed more than 20 ns from the falling edge of load. It is
preferrable that the falling edge of clock occurs before the falling edge of load.
FIGURE 2. Timing Diagram
www.national.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM1971MX | 功能描述:衰減器 -IC RoHS:否 制造商:Skyworks Solutions, Inc. 最大衰減:18 dB 容差: 阻抗: 功率額定值:30 dBm 安裝風(fēng)格:SMD/SMT 工作溫度范圍:- 40 C to + 85 C |
| LM1971MX/NOPB | 功能描述:衰減器 -IC RoHS:否 制造商:Skyworks Solutions, Inc. 最大衰減:18 dB 容差: 阻抗: 功率額定值:30 dBm 安裝風(fēng)格:SMD/SMT 工作溫度范圍:- 40 C to + 85 C |
| LM1971N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LM1971 Overture⑩ Audio Attenuator Series Digitally Controlled 62 dB Audio Attenuator with/Mute |
| LM1971N/NOPB | 功能描述:IC ATTENUATOR AUDIO W/MUTE 8-DIP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:Overture™ 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| LM1972 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Pot 2-Channel 78dB Audio Attenuator with Mute |
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