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參數資料
| 型號： | LM555CM |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | Single Timer |
| 中文描述： | PULSE; RECTANGULAR, TIMER, PDSO8 |
| 封裝： | SOP-8 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 79K |
| 代理商： | LM555CM |
SEMICONDUCT OR
8-3
Features
Accurate Timing From Microseconds Through Hours
Astable and Monostable Operation
Adjustable Duty Cycle
Output Capable of Sourcing or Sinking up to 200mA
Output Capable of Driving TTL Devices
Normally ON and OFF Outputs
High Temperature Stability . . . . . . . . . . . . . . 0.005%/oC
Directly Interchangeable with SE555, NE555, MC1555,
and MC1455
Applications
Precision Timing
Pulse Generation
Sequential Timing
Pulse Detector
Time Delay Generation
Pulse Width and Position
Modulation
Description
The CA555 and CA555C are highly stable timers for use in
precision timing and oscillator applications. As timers, these
monolithic integrated circuits are capable of producing accu-
rate time delays for periods ranging from microseconds
through hours. These devices are also useful for astable
oscillator operation and can maintain an accurately con-
trolled free running frequency and duty cycle with only two
external resistors and one capacitor.
The circuits of the CA555 and CA555C may be triggered by
the falling edge of the waveform signal, and the output of
these circuits can source or sink up to a 200mA current or
drive TTL circuits.
These types are direct replacements for industry types in
packages with similar terminal arrangements e.g. SE555
and NE555, MC1555 and MC1455, respectively. The CA555
type circuits are intended for applications requiring premium
electrical performance. The CA555C type circuits are
intended for applications requiring less stringent electrical
characteristics.
Ordering Information
PART NUMBER
(BRAND)
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
CA0555E
-55 to 125
8 Ld PDIP
E8.3
CA0555M (555)
-55 to 125
8 Ld SOIC
M8.15
CA0555M96 (555)
-55 to 125
8 Ld SOIC
M8.15
CA0555T
-55 to 125
8 Pin Metal Can
T8.C
CA0555CE
0 to 70
8 Ld PDIP
E8.3
CA0555CM (555C)
0 to 70
8 Ld SOIC
M8.15
CA0555CM96 (555C)
0 to 70
8 Ld SOIC
M8.15
CA0555CT
0 to 70
8 Pin Metal Can
T8.C
LM555N
-55 to 125
8 Ld PDIP
E8.3
LM555CN
0 to 70
8 Ld PDIP
E8.3
NE555N
0 to 70
8 Ld PDIP
E8.3
NOTE:
Denotes Tape and Reel
Pinouts
CA555, CA555C (PDIP, SOIC)
LM555, LM555C, NE555 (PDIP)
TOP VIEW
CA555, CA555C (METAL CAN)
TOP VIEW
Functional Block Diagram
GND
TRIGGER
OUTPUT
RESET
1
2
3
4
8
7
6
5
V+
DISCHARGE
THRESHOLD
CONTROL
VOLTAGE
V+
THRESHOLD
TRIGGER
RESET
GND
OUTPUT
DISCHARGE
CONTROL
2
4
6
1
3
7
5
8
TAB
VOLTAGE
THRESHOLD
COMPAR
6
THRESHOLD
8
V+
5
TRIGGER
COMPAR
2
CONTROL
VOLTAGE
TRIGGER
FLIP-FLOP
OUTPUT
3
OUTPUT
7
DISCHARGE
4
RESET
1
GND
May 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1997
CA555, CA555C,
LM555, LM555C, NE555
Timers for Timing Delays and Oscillator Application
in Commercial, Industrial and Military Equipment
File Number
834.4
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