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參數資料
| 型號： | LM6125 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | High Speed Buffer |
| 中文描述： | 高速緩沖 |
| 文件頁數： | 7/9頁 |
| 文件大小： | 261K |
| 代理商： | LM6125 |
Application Hints
POWER SUPPLY DECOUPLING
The method of supply bypassing is not critical for stability of
the LM6125 series buffers. However, their high current out-
put combined with high slew rate can result in significant
voltage transients on the power supply lines if much induc-
tance is present. For example, a slew rate of 900 V/μs into a
50
load produces a di/dt of 18 A/μs. Multiplying this by a
wiring inductance of 50 nH results in a 0.9V transient. To
minimize this problem use high quality decoupling very close
to the device. Suggested values are a 0.1 μF ceramic in par-
allel with one or two 2.2 μF tantalums. A ground plane is rec-
ommended.
LOAD IMPEDANCE
The LM6125 is stable into any load when driven by a 50
source. As shown in the Overshoot vs Capacitive Load
graph, worst case is a purely capacitive load of about
1000 pF. Shunting the load capacitance with a resistor will
reduce overshoot.
SOURCE INDUCTANCE
Like any high-frequency buffer, the LM6125 can oscillate at
high values of source inductance. The worst case condition
occurs at a purely capacitive load of 50 pF where up to
100 nH of source inductance can be tolerated. With a 50
load, this goes up to 200 nH. This sensitivity may be reduced
at the expense of a slight reduction in bandwidth by adding a
resistor in series with the buffer input.A100
resistor will en-
sure stability with source inductances up to 400 nH with any
load.
ERROR FLAG LOGIC
The Error Flag pin is an open-collector output which requires
an external pull-up resistor. Flag voltage is HIGH during op-
eration, and is LOW during a fault condition. A fault condition
occurs if either the internal current limit or the thermal shut-
down is activated, or the shutdown (S/D) pin is driven low by
external logic. Flag voltage returns to its HIGH state when
normal operation resumes.
If the S/D pin is not to be used, it should be connected to V
+
.
OVERVOLTAGE PROTECTION
The LM6125 may be severely damaged or destroyed if the
Absolute Maximum Rating of 7V between input and output
pins is exceeded.
If the buffer’s input-to-output differential voltage is allowed to
exceed
7V,
a
base-emitter
reverse-breakdown,
and
will
forward-biased base-emitter junction. Referring to the
LM6125 simplified schematic, the transistors involved are
Q1 and Q3 for positive inputs, and Q2 and Q4 for negative
inputs. If any current is allowed to flow through these junc-
tions, localized heating of the reverse-biased junction will oc-
cur, potentially causing damage. The effect of the damage is
typically increased offset voltage, increased bias current,
and/or degraded AC performance. The damage is cumula-
tive, and may eventually result in complete device failure.
The device is best protected by the insertion of the parallel
combination of a 100 k
resistor (R1) and a small capacitor
(C1) in series with the buffer input, and a 100 k
resistor
(R2) from input to output of the buffer (see Figure 1). This
network normally has no effect on the buffer output. How-
ever, if the buffer’s current limit or shutdown is activated, and
the output has a ground-referred load of significantly less
than 100 k
, a large input-to-output voltage may be present.
R1 and R2 then form a voltage divider, keeping the
input-output differential below the 7V Maximum Rating for in-
put voltages up to 14V. This protection network should be
sufficient to protect the LM6125 from the output of nearly any
op amp which is operated on supply voltages of
±
15V or
lower.
junction
be
will
be
with
in
a
in
series
DS009222-8
FIGURE 1. LM6125 with Overvoltage Protection
www.national.com
7
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