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參數資料
| 型號： | LM75AD,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 9/24頁 |
| 文件大小： | 137K |
| 描述： | IC TEMP SENSOR DIGITAL 8-SOIC |
| 特色產品： | NXP - I2C Interface |
| 標準包裝： | 100 |
| 功能： | 溫度監視系統（傳感器），監視器 |
| 傳感器類型： | 內部 |
| 感應溫度： | -55°C ~ 125°C |
| 精確度： | ±3°C（最小值） |
| 拓撲： | ADC（三角積分型），比較器，振蕩器，寄存器庫 |
| 輸出類型： | 2 線串行，I²C? |
| 輸出警報： | 無 |
| 輸出風扇： | 是 |
| 電源電壓： | 2.8 V ~ 5.5 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SO |
| 包裝： | 管件 |
| 產品目錄頁面： | 846 (CN2011-ZH PDF) |
| 配用： | 568-4002-ND - DEMO BOARD I2C |
| 其它名稱： | 568-4226-5 935269775112 LM75AD LM75AD-ND |
LM75A_4
?NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 10 July 2007
9 of 24
NXP Semiconductors
LM75A
Digital temperature sensor and thermal watchdog
When a set-point register is read, all 16 bits are provided to the bus and must be collected
by the controller to complete the bus operation. However, only the 9 most signicant bits
should be used and the 7 LSB of the LSByte are equal to zero and should be ignored.
T
ab
le
13 shows examples of the limit data and value.
7.5 OS output and polarity
The OS output is an open-drain output and its state represents results of the device
watchdog operation as described in
Section
7.1. In order to observe this output state, an
external pull-up resistor is needed. The resistor should be as large as possible, up to
200 k&, to minimize the Temp reading error due to internal heating by the high OS sinking
current.
The OS output active state can be selected as HIGH or LOW by programming bit B2
(OS_POL) of register Conf: setting bit OS_POL to logic 1 selects OS active HIGH and
setting bit B2 to logic 0 sets OS active LOW. At power-up, bit OS_POL is equal to logic 0
and the OS active state is LOW.
7.6 OS comparator and interrupt modes
As described in
Section
7.1, the device OS output responds to the result of the
comparison between register Temp data and the programmed limits, in registers Tos and
Thyst, in different ways depending on the selected OS mode: OS comparator or
OS interrupt. The OS mode is selected by programming bit B1 (OS_COMP_INT) of
register Conf: setting bit OS_COMP_INT to logic 1 selects the OS interrupt mode, and
setting to logic 0 selects the OS comparator mode. At power-up, bit OS_COMP_INT is
equal to logic 0 and the OS comparator is selected.
Table 11. Tos register
MSByte
LSByte
7 6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
Table 12. Thyst register
MSByte
LSByte
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
Table 13. Tos and Thyst limit data and value
11-bit binary
(2s complement)
Hexadecimal value
Decimal value
Value
0 1111 1010
0FA
250
+125.0 癈
0 0011 0010
032
50
+25.0 癈
0 0000 0001
001
1
+0.5 癈
0 0000 0000
000
0
0.0 癈
1 1111 1111
1FF
1
0.5 癈
1 1100 1110
1CE
50
25.0 癈
1 1001 0010
192
110
55.0 癈
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