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參數資料
| 型號： | LM84CIMQA |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | Diode Input Digital Temperature Sensor with Two-Wire Interface |
| 中文描述： | 二極管輸入數字溫度傳感器兩線接口 |
| 文件頁數： | 12/16頁 |
| 文件大小： | 168K |
| 代理商： | LM84CIMQA |
1.0 Functional Description
(Continued)
1.8 LM84 REGISTERS
1.8.1 COMMAND REGISTER
Selects which registers will be read from or written to. Data for this register should be transmitted during the Command Byte of
the SMBus write communication.
P7
0
P6
0
P5
0
P4
0
P3
P2
P1
P0
Command Select
P0-P7: Command Select:
Command Se-
lect Address
<
P7:P0
>
hex
Power On Default State
Register Name
Register Function
<
D7:D0
>
binary
<
D7:D0
>
deci-
mal
0
0
0
0
0
127
127
00h
01h
02h
03h
04h
05h
07h
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0111 1111
0111 1111
RLT
RRT
RS
RC
RMID
RLCS
RRCS
Read Local Temperature
Read Remote Temperature
Read Status
Read Configuration
Manufacturers ID
Read Local T_CRIT Setpoint
Read Remote T_CRIT
Setpoint
Write Configuration
Write Local T_CRIT Setpoint
Write Remote T_CRIT
Setpoint
09h
0Bh
0Dh
0000 0000
0111 1111
0111 1111
0
WC
WLCS
WRCS
127
127
1.8.2 LOCAL and REMOTE TEMPERATURE REGISTERS
(Read Only Address 00h and 01h):
D7
D6
D5
D4
MSB
Bit 6
Bit 5
Bit 4
D7–D0: Temperature Data. One LSB = 1C. Two’s complement format.
D3
Bit 3
D2
Bit 2
D1
Bit 1
D0
LSB
1.8.3 STATUS REGISTER
(Read Only Address 02h):
D7
D6
0
LTCRIT
Power up default is with all bits “0” (zero).
D2: OPEN: When set to 1 indicates a Remote Diode disconnect.
D4: RTCRIT: When set to 1 indicates an RT_CRIT alarm.
D6: LTCRIT: When set to 1 indicates an LT_CRIT alarm.
D7, D5, D3, D1–D0: These bits are always set to 0.
D5
0
D4
D3
0
D2
D1
0
D0
0
RTCRIT
OPEN
1.8.4 Manufacturers ID Register
(Read Address 04h) Default value 00h.
1.8.5 CONFIGURATION REGISTER
(Read Address 03h /Write Address 09h):
D7
T_CRIT_A
mask
Power up default is with all bits “0” (zero).
D7: T_CRIT_A mask: When set to 1 T_CRIT_A interrupts are masked.
D6–D0: These bits are always set to 0. A write of 1 will return a 0 when read.
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
L
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