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參數(shù)資料
| 型號(hào)： | LM9800CCV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | 8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 5/34頁(yè) |
| 文件大小： | 619K |
| 代理商： | LM9800CCV |
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AC Electrical Characteristics, MCLK Independent
(Continued)
The following specifications apply for AGND = DGND = DGND
= 0V, V
= V
= V
= +5.0V
, REF IN = +1.225V
DC
,
f
MCLK
= 20MHz, t
MCLK
= 1/f
MCLK
, t
r
= t
= 5ns, R
s
= 25
, C
L
(databus loading) = 50 pF/pin.
Boldface limits apply for T
A
T
J
MIN
to T
MAX
A
= T
J
= 25C.
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
t
DACC
Access Time Delay from RD Low to
DD0–DD7 Data Valid
Maximum SCLK Frequency
SCLK Duty Cycle
20
40
ns (max)
f
SCLK
2.5
40
60
MHz (max)
% (min)
% (max)
t
SDI
SDI Set-Up Time from SCLK
Rising Edge
SDI Hold Time from SCLK
Rising Edge
Delay from SCLK Falling Edge to
SDO Data Valid
SDO Hold Time from SCLK
Falling Edge
DELAY from SCLK Falling Edge to
CS Rising or Falling Edge
Set-Up Time of CS Rising or Falling
Edge to SCLK Rising Edge
Access Time Delay from CS Falling
Edge to SDO Data Valid
Delay from CS Rising Edge to SDO
TRI-STATE
SDO Rise Time, TRI-STATE to High
SDO Rise Time, Low to High
SDO Fall Time, TRI-STATE to Low
SDO Fall Time, High to Low
3
10
ns (min)
t
HDI
2
15
ns (min)
t
DDO
35
55
ns (max)
t
HDO
R
L
= 3K, C
L
= 25 pF
21
55
5
ns (max)
ns (min)
t
DELAY
2
5
ns (min)
t
SETUP
2
10
ns (min)
t
SACC
20
40
ns (max)
t
S1H
, t
S0H
R
L
= 3K, C
L
= 50 pF
40
100
ns (max)
t
RDO
R
L
= 3K, C
L
= 50 pF
20
20
20
20
ns
ns
ns
ns
t
FDO
R
L
= 3K, C
L
= 50 pF
5
www.national.com
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