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參數資料
型號: LM9811
廠商: National Semiconductor Corporation
英文描述: 10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor
中文描述: 10位Greyscale/30-Bit彩色線陣CCD傳感器處理器
文件頁數: 18/36頁
文件大?。?/td> 605K
代理商: LM9811
Configuration Register
t
= 1/f
= 1 MCLK period. Examples given in parenthesis are for f
MCLK
=
20MHz (t
MCLK
= 50ns). Times for 12MHz MCLK can be calculated by multiplying by
(Continued)
TABLE 2. Configuration Register Parameters
(Continued)
Parameter
Control Bits
BLS3
0
0
0
0
1
1
1
BLL4
0
0
0
0
1
1
1
GAIN4
0
0
0
1
1
1
Result
Dummy Pixels
Note:
Minimum
Register Value is 2.
Actual number of
dummy pixels in CCD
should be one less
than number in this
register.
BLS6
0
0
0
0
1
1
1
BLL7
0
0
0
0
1
1
1
GAIN7
0
0
0
1
1
1
BLS5
0
0
0
0
1
1
1
BLL6
0
0
0
0
1
1
1
GAIN6
0
0
0
1
1
1
BLS4
0
0
0
0
1
1
1
BLL5
0
0
0
0
1
1
1
GAIN5
0
0
0
1
1
1
BLS2
0
0
0
0
1
1
1
BLL3
0
0
0
0
1
1
1
GAIN3
0
0
0
1
1
1
BLS1
0
0
1
1
0
1
1
BLL2
0
0
0
0
1
1
1
GAIN2
0
0
0
1
1
1
BLS0
0
1
0
1
1
0
1
BLL1
0
0
1
1
0
1
1
GAIN1
0
0
1
0
1
1
Dummy Pixels
Not Valid
Not Valid
1
2
124
125
126
Optical Black Pixels
Not Valid
1
2
3
253
254
255
dB [V/V]
0.00 1.000
0.07 1.008
0.13 1.015
9.35 2.935
9.37 2.942
9.40 2.950
Optical Black Pixels
Note:
Minimum
Register Value is 1.
BLL0
0
1
0
1
1
0
1
GAIN0
0
1
0
1
0
1
Internal PGA
Gain Coefficient
PGA Gain
Coefficient
Source
PGASRC
0
1
ODSIGN
0
1
PD
0
1
OFF ADD
0
1
Internal
External
Offset DAC Sign
Negative
Positive
Power Down
Operating
Powered Down
Offset Add
Offset
z
0 LSB
Offset
z
+8 LSB
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