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參數(shù)資料
| 型號(hào)： | LM98501CCVBH |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 10-Bit, 27 MSPS Camera Signal Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁(yè)數(shù)： | 17/24頁(yè) |
| 文件大小： | 490K |
| 代理商： | LM98501CCVBH |
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Register Memory Map
Register Data
The following section describes all available registers in the
LM98501 register bank and their functions.
PGA GAIN REGISTERS
Register Name PGA Gain 0
Address
Type
Reset Value
0 Hex
Read/Write
0000 0000 Binary
Bit
[7:0]
Bit Symbol
PGA Gain
Description
0.0 dB–32.0 dB in 0.125 dB
steps.
Register Name PGA Gain 1
Address
Type
Reset Value
1 Hex
Read/Write
0000 0000 Binary
Bit
[7:0]
Bit Symbol
PGA Gain
Description
0.0 dB–32.0 dB in 0.125 dB
steps.
Register Name PGA Gain 2
Address
Type
Reset Value
2 Hex
Read/Write
0000 0000 Binary
Bit
[7:0]
Bit Symbol
PGA Gain
Description
0.0 dB–32.0 dB in 0.125 dB
steps.
Register Name PGA Gain 3
Address
Type
3 Hex
Read/Write
Reset Value
0000 0000 Binary
Bit
[7:0]
Bit Symbol
PGA Gain
Description
0.0 dB–32.0 dB in 0.125 dB
steps.
ANALOG OFFSET REGISTERS
Register Name Analog Offset 0
Address
Type
Reset Value
4 Hex
Read/Write
0000 0000 Binary
Bit
[7:0]
Bit Symbol
Signed Analog
Offset
Description
Digital representation of the
analog offset to be applied to
the input of the PGA. See
“Analog Offset” on page 15.
Register Name Analog Offset 1
Address
Type
Reset Value
5 Hex
Read/Write
0000 0000 Binary
Bit
[7:0]
Bit Symbol
Signed Analog
Offset
Description
Digital representation of the
analog offset to be applied to
the input of the PGA. See
“Analog Offset” on page 15.
Register Name Analog Offset 2
Address
Type
Reset Value
6 Hex
Read/Write
0000 0000 Binary
Title
Address
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Default Value
0000 0000 (0d)
0000 0000 (0d)
0000 0000 (0d)
0000 0000 (0d)
0000 0000 (0d)
0000 0000 (0d)
0000 0000 (0d)
0000 0000 (0d)
0000 0000 (0d)
0000 0000 (0d)
XXXX 0000 (0d)
0001 0000 (32d)
0100 1110 (78d)
XX00 0X00 (0d)
1010 1010 (170d)
0101 1010 (90d)
PGA Gain 0
PGA Gain 1
PGA Gain 2
PGA Gain 3
Analog Offset 0
Analog Offset 1
Analog Offset 2
Analog Offset 3
CFA Configuration 0
CFA Configuration 1
CFA Definition
Output Black Level
Software Control 0
Software Control 1
Power Level Control 0
Power Level Control 1
FIGURE 12. Register Memory Map
L
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| LM98501 | 10-Bit, 27 MSPS Camera Signal Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM98501VBH WAF | 制造商:Texas Instruments 功能描述: |
| LM98502A WAF | 制造商:Texas Instruments 功能描述: |
| LM98503 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit, 18 MSPS Camera Signal Processor |
| LM98503CCVV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit, 18 MSPS Camera Signal Processor |
| LM98510CCMT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
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