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參數(shù)資料
| 型號： | LMA2010 |
| 廠商： | Logic Devices Incorporated |
| 英文描述： | 16 x 16-Bit Multiplier-Accumulator(16x 16位乘法器-累加器) |
| 中文描述： | 16 × 16位乘法累加器（16x的16位乘法器-累加器） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 192K |
| 代理商： | LMA2010 |
DEVICES INCORPORATED
LMA1010/2010
16 x 16-bit Multiplier-Accumulator
16 x 16-bit Multiplier-Accumulator
Multiplier-Accumulators
08/16/2000–LDS.10/2010-P
1
K
20 ns Multiply-Accumulate Time
K
Replaces Fairchild TMC2210,
Cypress CY7C510, IDT 7210L,
and AMD Am29510
K
Two’s Complement or Unsigned
Operands
K
Accumulator Performs Preload,
Accumulate, and Subtract
K
Three-State Outputs
K
68-pin PLCC, J-Lead
FEATURES
DESCRIPTION
DEVICES INCORPORATED
The
LMA1010
and
LMA2010
are
high-speed,
low
multiplier-accumulators. The LMA1010
and LMA2010 are functionally identical;
they differ only in packaging. Full mili-
tary ambient temperature range opera-
tion is achieved with advanced CMOS
technology.
power
16-bit
The LMA1010 and LMA2010 produce
the 32-bit product of two 16-bit numbers.
The results of a series of multiplications
may be accumulated to form the sum of
products. Accumulation is performed to
35-bit precision with the multiplier prod-
uct sign extended as appropriate.
Data present at the A and B input regis-
ters is latched on the rising edges of
CLK A and CLK B respectively. RND,
TC, ACC, and SUB controls are latched
on the rising edge of the logical OR of
CLK A and CLK B. TC specifies the
input as two’s complement
(TC HIGH) or unsigned magnitude
(TC LOW). RND, when HIGH, adds ‘1’
to the most significant bit position of
the least significant half of the product.
Subsequent truncation of the 16 least
significant bits produces a result
correctly rounded to 16-bit preci-
sion.
ACC and SUB control accumulator
operation. ACC HIGH results in
addition of the multiplier product and
the accumulator contents, with the result
stored in the accumulator register on the
rising edge of CLK R. ACC and SUB
HIGH results in subtraction of the
accumulator contents from the
multiplier product, with the result stored
in the accumulator register. With ACC
LOW and SUB LOW, no accumulation
occurs and the next product is loaded
directly into the accumulator register.
ACC LOW and SUB HIGH is undefined.
The LMA1010/2010 output register
(accumulator register) is divided into
three independently controlled sec-
tions. The least significant result
(LSR) and most significant result
(MSR) registers are 16 bits in length.
The extended result register (XTR) is
3 bits long. The output signals R
15-0
and input signals B
15-0
share the same
bidirectional pins.
Each output register has an indepen-
dent output enable control. In addition
to providing three-state control of the
output buffers, when OEX, OEM, or OEL
are HIGH and PREL is HIGH, data can be
preloaded via the bidirectional output
pins into the respective output registers.
Data present on the output pins is
latched on the rising edge of CLK R. The
interrelation of PREL and the enable
controls is summarized in Table 1.
LMA1010/2010 B
LOCK
D
IAGRAM
A REGISTER
B REGISTER
16
16
A
15-0
B
15-0
R
15-0
ACC
SUB
REGISTER
R
CLK A
CLK B
RND
TC
32
R
31-16
16
R + A
R – A
PASS R
LEM
LEL
LEX
16
R
34-32
3
35
PRELOAD
CONTROL
LOGIC
3
CLK R
ACCUMULATOR
R
A
OEL
OEX
OEM
PREL
LEL
LEX
OEL
OEX
OEM
OEX
OEM
OEL
3
35
3
16
16
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相關(guān)代理商/技術(shù)參數(shù) |
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| LMA2010JC20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier/Accumulator |
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| LMA2010JC45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier/Accumulator |
| LMA2010JC55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier/Accumulator |
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