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參數資料
| 型號： | LMC6684BIN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運算放大器 |
| 英文描述： | Low Voltage, Rail-To-Rail Input and Output CMOS |
| 中文描述： | QUAD OP-AMP, 3000 uV OFFSET-MAX, 1.2 MHz BAND WIDTH, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數： | 9/24頁 |
| 文件大小： | 750K |
| 代理商： | LMC6684BIN |
AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
= 25C, V
+
= 3V, V = 0V, V
CM
= V
O
= V
+
/2, V
PD
= 0.6V and R
L
>
1
M
.
Boldface
limits apply at the temperature extremes (Note 16).
Symbol
Parameter
Conditions
Typ
(Note 5)
LMC6681AI
LMC6682AI
LMC6684AI
Limit
(Note 6)
200
LMC6681BI
LMC6682BI
LMC6684BI
Limit
(Note 6)
200
Units
t
ON
Time Delay for
Device to Power ON
Time Delay for
Device to Power OFF
Slew Rate
(Note 15)
50
μs
t
OFF
(Note 15)
0.5
2
2
μs
SR
(Note 8)
1.2
0.7
0.55
0.7
0.55
0.7
0.55
0.7
0.55
V/μs
min
V
+
= 10V, (Note 10)
1.2
GBW
φ
m
G
m
Gain-Bandwidth Product
Phase Margin
Gain Margin
Amp-to-Amp Isolation
Input-Referred
1.2
50
12
130
32
MHz
Deg
dB
dB
V
+
= 10V (Note 9)
f = 1 kHz
V
CM
= 0.5V
f = 1 kHz
e
n
Voltage Noise
i
n
Input-Referred
0.5
Current Noise
T.H.D.
Total Harmonic Distortion
f = 1 kHz, A
V
= +1
R
L
= 10 k
, V
O
= 2 V
PP
0.01
%
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is in-
tended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the electrical characteristics.
Note 2:
Human body model, 1.5 k
in series with 100 pF.
Note 3:
Applies to both single-supply and split-supply operation. Continous short circuit operation at elevated ambient temperature can result in exceeding the maxi-
mum allowed junction temperature of 150C. Output current in excess of
±
30 mA over long term may adversely affect reliability.
Note 4:
The maximum power dissipation is a function of T
,
θ
, and T
A
. The maximum allowable power dissipation at any ambient temperature is P
D
=(T
J(max)
T
A
)/
θ
JA
. All numbers apply for packages soldered directly into a PC board.
Note 5:
Typical Values represent the most likely parametric norm.
Note 6:
All limits are guaranteed by testing or statistical analysis.
Note 7:
V
+
= 3V, V
CM
= 0.5V. For sourcing and sinking, 0.5V
≤
V
O
≤
2.5V.
Note 8:
V
+
= 3V. Connected as Voltage Follower with 2V step input, and the output is measured from 15%–85%. Number specified is the slower of the positive or
negative slew rates.
Note 9:
Input referred, V
+
= 10V, and R
L
= 100 k
connected to 5V. Each amp excited in turn with 1 kHz to produce V
O
= 2 V
PP
.
Note 10:
V
+
=10V. Connected as voltage follower with 8V step Input, and output is measured from 15%–85%. Number specified is the slower of the positive or nega-
tive slew rates.
Note 11:
Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
Note 12:
Guaranteed limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
Note 13:
CMRR
+
and CMRR
are tested, and the number indicated is the lower of the two values. For CMRR
+
, V
+
/2
<
V
CM
<
V
+
for 1.8V, 2.2V, 3V, 5V, and 10V.
For CMRR
, 0
<
V
CM
V
+
/2 for 3V, 5V and 10V. For 1.8V and 2.2V, 0.25
V
CM
V
0.3.
Note 14:
V
+
= 10V, V
CM
= 0.5V. For Sourcing tests, 1V
≤
V
O
≤
5V. For Sinking tests, 5V
≤
V
O
≤
9V.
Note 15:
The propogation delays are measured using an input waveform of f = 5 Hz, and magnitude of 2.4V. Refer to Section 6.3 and Figures 14, 15 for a detailed
explanation.
Note 16:
The V
(threshold low and threshold high) limits are guaranteed at room temperature and at temperature extremes. Room temperature limits are produc-
tion tested. Limits at temperature extremes are guaranteed via correlation using temperature regression analysis methods. Refer to Section 6.2 for an overview of
the threshold voltages.
www.national.com
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