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參數(shù)資料
型號(hào): LMC7221BIM5X
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 運(yùn)動(dòng)控制電子
英文描述: Tiny CMOS Comparator with Rail-To-Rail Input and Open Drain Output
中文描述: COMPARATOR, 18000 uV OFFSET-MAX, 7000 ns RESPONSE TIME, PDSO5
封裝: SOT-23, 5 PIN
文件頁(yè)數(shù): 4/12頁(yè)
文件大小: 271K
代理商: LMC7221BIM5X
AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
J
= 25C, V
+
= 5V, V
= 0V, V
CM
= V
O
= V
+
/2.
Boldface
limits apply at
the temperature extreme
Typ
LMC7221AI
Limit
(Note 6)
LMC7221BI
Limit
(Note 6)
Symbol
Parameter
Conditions
(Note 5)
Units
t
rise
Rise Time
f = 10 kHz, C
L
= 50 pF, (Note 9)
Overdrive = 10 mV, 5 k
Pullup
f = 10 kHz, C
L
= 50 pF, (Note 9)
Overdrive = 10 mV, 5 k
Pullup
f = 10 kHz,
C
L
= 50 pF,
5 k
Pullup
(Note 9)
V+ = 2.7V,
f = 10 kHz,
C
L
= 50 pF,
5 k
Pullup
(Note 9)
f = 10 kHz,
C
L
= 50 pF,
5 k
Pullup
(Note 9)
V+ = 2.7V,
f = 10 kHz,
C
L
= 50 pF,
5 k
Pullup
(Note 9)
0.3
μs
t
fall
Fall Time
0.3
μs
t
PHL
Propagation Delay
(High to Low)
(Note 11)
10 mV
100 mV
10
4
μs
10 mV
10
μs
100 mV
4
t
PLH
Propagation Delay
(Low to High)
(Note 11)
10 mV
100 mV
6
4
μs
10 mV
7
μs
100 mV
4
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in-
tended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2:
Human body model, 1.5 k
in series with 100 pF.
Note 3:
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150C. Output currents in excess of
±
30 mA may adversely affect reliability.
Note 4:
The maximum power dissipation is a function of T
J(max)
,
θ
JA
, and T
A
. The maximum allowable power dissipation at any ambient temperature is
Note 5:
P
D
= (T
J(max)
T
A
)/
θ
JA
. All numbers apply for packages soldered directly into a PC board.
Note 6:
Typical values represent the most likely parametric norm.
Note 7:
All limits are guaranteed by testing or statistical analysis.
Note 8:
Limiting input pin current is only necessary for input voltages which exceed the absolute maximum input voltage rating.
Note 9:
Do not short circuit the output to V+ when V+ is greater than 12V or reliability will be adversely affected.
Note 10:
C
L
includes the probe and test jig capacitance.
Note 11:
Input offset voltage average drift is calculated by dividing the accelerated operating life V
OS
drift by the equivalent operational time. This represents worst
case input conditions and includes the first 30 days of drift.
Note 12:
Input step voltage for propagation delay measurement is 2V.
www.national.com
4
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