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參數資料
| 型號： | LMH6672MAX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運算放大器 |
| 英文描述： | Dual, High Output Current, High Speed Op Amp |
| 中文描述： | DUAL OP-AMP, 4000 uV OFFSET-MAX, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數： | 12/14頁 |
| 文件大?。?/td> | 599K |
| 代理商： | LMH6672MAX |
Application Notes
Thermal Management
The LMH6672 is a high-speed, high power, dual operational
amplifier with a very high slew rate and very low distortion.
For ease of use, it uses conventional voltage feedback.
These characteristics make the LMH6672 ideal for applica-
tions where driving low impedances of 25-100
such as
xDSL and active filters.
A class AB output stage allows the LMH6672 to deliver high
currents to low impedance loads with low distortion while
consuming low quiescent supply current. For most op-amps,
class AB topology means that internal power dissipation is
rarely an issue, even with the trend to smaller surface mount
packages. However, the LMH6672 has been designed for
applications where high levels of power dissipation may be
encountered.
Several factors contribute to power dissipation and conse-
quently higher junction temperatures. These factors need to
be well understood if the LMH6672 is to perform to specifi-
cations in all applications. This section will examine the
typical application that is shown on the front page of this data
sheet as an example. (Figure 1) Because both amplifiers are
in a single package, the calculations will for the total power
dissipated by both amplifiers.
There are two separate contributors to the internal power
dissipation:
1. The product of the supply voltage and the quiescent
current when no signal is being delivered to the external
load.
2. The additional power dissipated while delivering power
to the external load.
The first of these components appears easy to calculate
simply by inspecting the data sheet. The typical quiescent
supply current for this part is 6.2mA per amplifier, therefore,
with a (6 volt supply, the total power dissipation is:
P
D
= V
S
x 2 x l
Q
= 12 x (12.4x10
-3
) = 149 mW
(V
S
= V
CC
+ V
EE
)
With a thermal resistance of 172C/W for the SOIC package,
this level of internal power dissipation will result in a junction
temperature (T
J
) of 26C above ambient.
Using the worst-case maximum supply current of 18mA and
an ambient of 85C, a similar calculation results in a power
dissipation of 216 mW, or a T
J
of 122C.
This is approaching the maximum allowed T
of 150C be-
fore a signal is applied. Fortunately, in normal operation, this
term is reduced, for reasons that will soon be explained.
The second contributor to high T
is the power dissipated
internally when power is delivered to the external load. This
cause of temperature rise is more difficult to calculate, even
when the actual operating conditions are known.
To maintain low distortion, in a ClassAB output stage, an idle
current, I
Q
, is maintained through the output transistors
when there is little or no output signal. In the LMH6672,
about 4.8 mAof the total quiescent supply current of 12.4 mA
flows through the output stages.
Under normal large signal conditions, as the output voltage
swings positive, one transistor of the output pair will conduct
the load current, while the other transistor shuts off, and
dissipates no power. During the negative signal swing this
situation is reversed, with the lower transistor sinking the
load current while the upper transistor is cut off. The current
in each transistor will approximate a half wave rectified
version of the total load current.
Because the output stage idle current is now routed into the
load, 4.8mA can be subtracted from the quiescent supply
current when calculating the quiescent power when the out-
put is driving a load.
The power dissipation caused by driving a load in a DSL
application, using a 1:2 turns ratio transformer driving 20
mW into the subscriber line and 20mW into the back termi-
nation resistors, can be calculated as follows:
P
DRIVER
= P
TOT
– (P
TERM
+ P
LINE
) where
P
DRIVER
is the LMH6672 power dissipation
P
TOT
is the total power drawn from the power supply
P
is the power dissipated in the back termination resis-
tors
P
LINE
is the power sent into the subscriber line
At full specified power, P
TERM
= P
LINE
= 20mW, P
TOT
= V
S
x I
S
.
In this application, V
S
= 12V.
I
S
= I
Q
+ A
VG
|I
OUT
|.
I
= the LMH6672 quiescent current minus the output stage
idle current.
I
Q
= 12.4 - 4.8 = 7.6mA
A
|I
| for a full-rate ADSL CPE application, using a 1:2
turns ratio transformer, is
For a Gaussian signal, which the DMT ADSL signal approxi-
mates, A
VG
|I
OUT
| =
= (22.6mA + 7.6mA) x 12V = 362mW and P
DRIVER
is 362-40
= 322mW.
In the SOIC package, with a
θ
JA
of 172C/W, this causes a
temperature rise of 55C. With an ambient temperature at
the maximum recommended 85C, the T
J
is at 140C, well
below the specified 150C maximum.
Even if we assume the absolute maximum I
over tempera-
ture of 18mA, when we scale up the I
proportionally to 7mA,
the P
DRIVER
only goes up by 41mW causing a 62C rise to
147C.
Although very few CPE applications will ever operate in an
environment as hot as 85C, if a lower T
is desired or the
LMH6672 is to be used in an application where the power
dissipation is higher, the PSOP package provides a much
lower
θ
JA
of only 58.6C/W.
Using the same P
as above, we find that the tempera-
ture rise is only 19 and 21C, resulting in T
J
’s in an 85C
ambient of 104C and 106C respectively.
Circuit Layout Considerations
National Semiconductor suggests the following evaluation
boards as a guide for high frequency layout and as an aid in
device testing and characterization. Since the exposed PAD
(or DAP) of the PSOP and LLP package is internally floating,
the footprint for DAP could be connected to ground plane in
PCB for better heat dissipation.
= 28.28mA RMS.
= 22.6mA. Therefore, P
TOT
Device
Package
Evaluation
Board PN
CLC730036
CLC730114
CLC730121
LMH6672MA
LMH6672LD
LMH6672MR
8-Pin SOIC
8-Pin LLP
8-Pin PSOP
These free evaluation boards are shipped when a device
sample request is placed with National Semiconductor.
L
www.national.com
12
相關PDF資料 |
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| LMH6672MR | Dual, High Output Current, High Speed Op Amp |
| LMH6672MRX | Dual, High Output Current, High Speed Op Amp |
| LMH6672LDX | Silver Mica Capacitor; Capacitance:3300pF; Capacitance Tolerance: 5%; Series:CDV30; Voltage Rating:1500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:11.1mm; Leaded Process Compatible:No RoHS Compliant: No |
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相關代理商/技術參數 |
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|---|---|
| LMH6672MAX/NOPB | 功能描述:運算放大器 - 運放 RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LMH6672MR | 功能描述:運算放大器 - 運放 RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LMH6672MR | 制造商:Texas Instruments 功能描述:AMP HIGH SPD HIGH O/P DUAL SOIC8 |
| LMH6672MR/NOPB | 功能描述:運算放大器 - 運放 Dual, Hi Output Curr Hi Speed Op Amp RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LMH6672MRX | 功能描述:運算放大器 - 運放 RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
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