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參數(shù)資料
| 型號： | LMU216JC20 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | 16 x 16-bit Parallel Multiplier |
| 中文描述： | 16-BIT, DSP-MULTIPLIER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 188K |
| 代理商： | LMU216JC20 |
DEVICES INCORPORATED
LMU16/216
16 x 16-bit Parallel Multiplier
16 x 16-bit Parallel Multiplier
Multipliers
08/16/2000–LDS.16/216-N
1
K
20 ns Worst-Case Multiply Time
K
Low Power CMOS Technology
K
Replaces Fairchild MPY016/TMC216,
Cypress CY7C516, IDT 7216L, and
AMD Am29516
K
Two’s Complement, Unsigned, or
Mixed Operands
K
Three-State Outputs
K
68-pin PLCC, J-Lead
FEATURES
DESCRIPTION
DEVICES INCORPORATED
The
LMU16
and
LMU216
are high-
speed, low power 16-bit parallel
multipliers. The LMU16 and
LMU216 are functionally identical;
they differ only in packaging.
The LMU16 and LMU216 produce
the 32-bit product of two 16-bit
numbers. Data present at the A
inputs, along with the TCA control
bit, is loaded into the A register on
the rising edge of CLK A. B data
and the TCB control bit are
similarly loaded by CLK B. The
TCA and TCB controls specify the
A and B operands as two’s
complement when HIGH, or
unsigned magnitude when LOW.
RND is loaded on the rising edge of
the logical OR of CLK A and CLK B.
RND, when HIGH, adds ‘1’ to the
most significant bit position of the
least significant half of the product.
Subsequent truncation of the 16 least
significant bits produces a result
correctly rounded to 16-bit precision.
At the output, the Right Shift control
(RS) selects either of two output
formats. RS LOW produces a 31-bit
product with a copy of the sign bit
inserted in the MSB postion of the
least significant half. RS HIGH gives a
full 32-bit product. Two 16-bit output
registers are provided to hold the
most and least significant halves of the
result (MSP and LSP) as defined by
RS. These registers are loaded on the
rising edge of CLK M and CLK L
respectively. For asynchronous
output, these registers may be made
transparent by setting the feed
through control (FT) HIGH.
The two halves of the product may be
routed to a single 16-bit three-state
output port (MSP) via a multiplexer.
MSPSEL LOW causes the MSP
outputs to be driven by the most
significant half of the result. MSPSEL
HIGH routes the least significant half
of the result to the MSP outputs. In
addition, the LSP is available via the B
port through a separate three-state
buffer.
The output multiplexer control
MSPSEL uses a pin which is a supply
ground in the Fairchild MPY016H/
TMC216H. When this control is LOW
(GND), the function is that of the
MPY016H/TMC216H, thus allowing
full compatibility.
LMU16/216 B
LOCK
D
IAGRAM
A REGISTER
B REGISTER
REGISTER
RESULT
R
CLK A
CLK B
RND
FT
16
16
32
16
16
16
OEM
OEL
A
15-0
R
31-16
TCA
TCB
RS
CLK M
FORMAT ADJUST
16
B
15-0
/
R
15-0
MSPSEL
CLK L
相關PDF資料 |
PDF描述 |
|---|---|
| LMU216JC25 | 16 x 16-bit Parallel Multiplier |
| LMU217JC25 | GIGATRUE 550 CAT PATCH CBL NO BOOT 30FT YW 25 PK |
| LMU217JC35 | GIGATRUE 550 CAT6 PATCH 50 FT, NON BOOT, YELLOW |
| LMU217 | 16 x 16-bit Parallel multiplier |
| LMU8UJC35 | 8 x 8-bit Parallel Multiplier |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LMU216JC25 | 制造商:LOGIC 制造商全稱:LOGIC 功能描述:16 x 16-bit Parallel Multiplier |
| LMU216JC35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
| LMU216JC45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
| LMU216JC55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
| LMU216JC65 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
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