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參數(shù)資料
| 型號(hào)： | LMV422 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual Rail-to-Rail Output Operational Amplifier with |
| 中文描述： | 雙軌至軌輸出運(yùn)算放大器 |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大小： | 761K |
| 代理商： | LMV422 |
Application Information
The LMV422 is a dual rail-to-rail output amplifier that can be
switched between two active power modes. The power se-
lect pin (PS) provides a method to optimize the power con-
sumption, bandwidth and short circuit current. When the PS
pin is set to greater than 4.5V (
Figure 1a
) or left open, the
LMV422 is in Low Power Mode operating at a bandwidth of
27 kHz and consuming only 2 μA of supply current per
channel. Setting the PS pin to less than 0.5V, switches the
LMV422 to Full Power Mode with a bandwidth of 8 MHz and
supply current of 400 uA per channel (
Figure 2b
).. The PS
pin should not exceed the supply voltage. The active power
modes of the two amplifiers can be set independently.
The LMV422 PS pin has an internal pull up and a logic level
control gate that makes it easy for the PS pin to be controlled
by the output of a logic gate or the output pin of a microcon-
troller. The following figures show the three typical output
configurations for logic gates and microcontrollers.
CAPACITIVE LOAD TOLERANCE
The LMV422 is optimized for maximum bandwidth when
operating at a minimum closed loop gain of +2 or 1, there-
fore, it is not recommended to be configured as a buffer. Like
many other op amps, the LMV422 may oscillate when the
applied load appears capacitive. The threshold of the oscil-
lation varies both with load and circuit gain (see Phase
Margin vs. Gain for various capacitive loads curves). The
load capacitance interacts with the amplifier’s output resis-
tance to create an additional pole. If this pole frequency is
too low, it will degrade the amplifier’s phase margin so that
the amplifier is no longer stable.
Figure 3a
and 3b show the addition of a small value resistor
R
ISO
or R
X
(50
to 100
) in series with the op amps output.
Figure 3b
shows the addition of a capacitor C
F
(5 pF to 10
pF) between the inverting input and the output pin. This
addition capacitor returns the phase margin to a safe value
without interfering with lower frequency circuit operation.
Note that in all cases, the output will ring heavily when the
load capacitance is near the threshold for oscillation.
20109807
Figure 1a Low Power Mode
20109808
Figure 1b Full Power Mode
FIGURE 1.
20109809
Figure 2a
20109810
Figure 2b
20109811
Figure 2c
FIGURE 2.
L
www.national.com
8
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