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參數資料
| 型號： | LMX2305TM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinumTM 550 MHz Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 550 MHz, PDSO20 |
| 封裝： | 0.173 INCH, PLASTIC, TSSOP-20 |
| 文件頁數： | 2/14頁 |
| 文件大小： | 228K |
| 代理商： | LMX2305TM |
Connection Diagram
LMX2305
TL/W/12459–2
20-Lead (0.173
×
Wide) Thin Shrink
Small Outline Package (TM)
Order Number LMX2305TM or LMX2305TMX
See NS Package Number MTC20
Pin Descriptions
Pin No.
Pin Name
I/O
Description
1
OSC
IN
I
Oscillator input. A CMOS inverting gate input intended for connection to a crystal resonator for
operation as an oscillator. The input has a V
CC
/2 input threshold and can be driven from an
external CMOS or TTL logic gate. May also be from a reference oscillator.
3
OSC
OUT
V
P
V
CC
O
Oscillator output.
Power supply for charge pump. Must be
t
V
CC
.
Power supply voltage input. Input may range from 2.65V to 5.5V. Bypass capacitors should be
placed as close as possible to this pin and be connected directly to the ground plane.
4
5
6
D
o
O
Internal charge pump output. For connection to a loop filter for driving the input of an external
VCO.
7
GND
Ground.
8
LD
O
Lock detect. Output provided to indicate when the VCO frequency is in ‘‘lock’’. When the loop is
locked, the pin’s output is HIGH with narrow low pulses.
10
f
IN
CLOCK
I
Prescaler input. Small signal input from the VCO.
11
I
High impedance CMOS Clock input. Data is clocked in on the rising edge, into the various
counters and registers.
13
DATA
I
Binary serial data input. Data entered MSB first. LSB is control bit. High impedance CMOS input.
14
LE
I
Load enable input (with internal pull-up resistor). When LE transitions HIGH, data stored in the
shift registers is loaded into the appropriate latch (control bit dependent). Clock must be low
when LE toggles high or low. See Serial Data Input Timing Diagram.
15
FC
I
Phase control select (with internal pull-up resistor). When FC is LOW, the polarity of the phase
comparator and charge pump combination is reversed.
16
BISW
O
Analog switch output. When LE is HIGH, the analog switch is ON, routing the internal charge
pump output through BISW (as well as through D
o
).
Monitor pin of phase comparator input. CMOS output.
17
f
OUT
w
p
O
18
O
Output for external charge pump.
w
p
is an open drain N-channel transistor and requires a pull-up
resistor.
19
PWDN
I
Power Down (with internal pull-up resistor).
PWDN
e
HIGH for normal operation.
PWDN
e
LOW for power saving.
Power down function is gated by the return of the charge pump to a TRI-STATE condition.
20
w
r
NC
O
Output for external charge pump.
w
r
is a CMOS logic output.
No connect.
2,9,12
http://www.national.com
2
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LMX2305TMX | 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2305WG/B | 制造商:Rochester Electronics LLC 功能描述: |
| LMX2306 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Power Frequency Synthesizer for RF Personal Communications |
| LMX2306_04 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Power Frequency Synthesizer for RF Personal Communications |
| LMX2306LBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FREQUENCY SYNTHESIZER|BICMOS|LLCC|16PIN|PLASTIC |
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