- 您現在的位置：買賣IC網 > PDF目錄361044 > LMX2354 (National Semiconductor Corporation) PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer PDF資料下載
參數資料
| 型號： | LMX2354 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| 中文描述： | PLLatinum小數分頻射頻/中頻整數雙低功耗頻率合成器? |
| 文件頁數： | 13/23頁 |
| 文件大小： | 403K |
| 代理商： | LMX2354 |
Programming Description
3.0 INPUT DATA REGISTER
The descriptions below describe the 24-bit data register loaded through the MICROWIRE Interface. The data register is used to
program the 15-bit IF_R counter register, and the 15-bit RF_R counter register, the 15-bit IF_N counter register, and the 19-bit
RF_N counter register. The data format of the 24-bit data register is shown below. The control bits CTL [1:0] decode the internal
register address. On the rising edge of LE, data stored in the shift register is loaded into one of 4 appropriate latches (selected
by address bits). Data is shifted in MSB first
MSB
LSB
DATA [21:0]
CTL [1:0]
23
2 1
0
3.1 Register Location Truth Table
CTL [1:0]
DATA Location
1
0
0
1
1
0
0
1
0
1
IF_R register
IF_N register
RF_R register
RF_N register
3.2 Register Content Truth Table
First Bit
REGISTER BIT LOCATION
16 15 14 13 12 11 10
Last Bit
2
c1
23
22
21 20 19
18
17
9
8
7
6
5
4
3
1
0
c2
IF_R
IF_N
OSC
IF_CTL_WORD
FRAC_16
FoLD
IF_CP_WORD
CMOS OUTPUTS/
FRAC TEST
RF_CP_WORD
IF_R_CNTR
0 0
IF_NB_CNTR
IF_NA_CNTR 0 1
RF_R DLL_MODE
RF_N
V2_EN
RF_R_CNTR
B_WORD
1 0
1 1
RF_CTL_WORD
C_WORD
A_WORD
FRAC_CNTR
4.0 PROGRAMMABLE REFERENCE DIVIDERS
4.1 IF_R REGISTER
If the Control Bits (CTL [1:0]) are 0 0, when data is transferred from the 24-bit shift register into a latch when LE is transitioned
high. This register determines the IF R counter value, IF Charge pump current, FoLD pin output, fractonal modulus, and oscillator
mode.
MSB
OSC
23
LSB
0
0
FRAC_16
22
FoLD [2:0]
21
IF_CP_WORD [1:0]
19 18
IF_R_CNTR [14:0]
17 16
0
2 1
4.1.1 OSC
The
OSC
bit, IF_R [23], selects whether the oscillator inputs OSC
and OSC
drive the IF and RF R counters separately or by
a common input signal path. When OSC = 0 , the OSC
pin drives the IF R counter while the OSC
RF
pin drives the RF R counter.
When the OSC = 1, the OSC
IF
pin drives both R counters.
(IF_R[23])
4.1.2 FRAC_16
The
FRAC_16
bit, IF_R [22], is used to set the fractional compensation at either 1/16 and 1/15 resolution. When FRAC-16 is set
to one, the fractional modulus is set to 1/16 resolution, and FRAC_16 = 0 corresponds to 1/15 (See section 5.2.3).
(IF_R[22])
L
www.national.com
13
相關PDF資料 |
PDF描述 |
|---|---|
| LMX2355TM | PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2354SLB | PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2355SLB | PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2430 | PLLatinum Dual High Frequency Synthesizer for RF Personal Communications |
| LMX2433TM | PLLatinum Dual High Frequency Synthesizer for RF Personal Communications |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LMX2354SLB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2354SLBX | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| LMX2354SLBX/NOPB | 功能描述:IC FREQ SYNTH DUAL 24-LAMCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2354SLDX | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| LMX2354SLEX | 制造商:Texas Instruments 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。