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參數資料
| 型號： | LP3982ILD-3.0 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Micropower, Ultra Low-Dropout, Low-Noise, 300mA CMOS Regulator |
| 中文描述： | 3 V FIXED POSITIVE LDO REGULATOR, 0.22 V DROPOUT, DSO8 |
| 封裝： | LLP-8 |
| 文件頁數： | 9/12頁 |
| 文件大?。?/td> | 361K |
| 代理商： | LP3982ILD-3.0 |
Application Information
(Continued)
The delay time for the application of
Figure 5
is set as
follows:
The application is set for a reset delay time of 8.8ms. Note
that the comparator should have high impedance inputs so
as to not load down the V
REF
at the CC pin of the LP3982.
Shutdown
The LP3982 goes into sleep mode when the SHDN pin is in
a logic low condition. During this condition, the pass transis-
tor, error amplifier, and bandgap are turned off, reducing the
supply current to 1nA typical. The maximum guaranteed
voltage for a logic low at the SHDN pin is 0.4V. A minimum
guaranteed voltage of 2V at the SHDN pin will turn the
LP3982 back on. The SHDN pin may be directly tied to V
IN
to
keep the part on. The SHDN pin may exceed V
IN
but not the
ABS MAX of 6.5V.
Figure 6
shows an application that uses the SHDN pin. It
detects when the battery is too low and disconnects the load
by turning off the regulator. A micropower comparator
(LMC7215) and reference (LM385) are combined with resis-
tors to set the minimum battery voltage. At the minimum
battery voltage, the comparator output goes low and tuns off
the LP3982 and corresponding load. Hysteresis is added to
the minimum battery threshold to prevent the battery’s re-
covery voltage from falsely indicating an above minimum
condition. When the load is disconnected from the battery, it
automatically increases in terminal voltage because of the
reduced IR drop across its internal resistance. The Minimum
battery detector of figure 6 has a low detection threshold
(V
) of 3.6V that corresponds to the minimum battery volt-
age. The upper threshold (V
) is set for 4.6V in order to
exceed the recovery voltage of the battery.
Resistor value for V
UT
and V
LT
are determined as follows:
(The application of figure 6 used a G
T
of 5μ mho)
The above procedure assumes a rail-to-rail output compara-
tor. Essentially, R
2
is in parallel with R
1
prior to reaching the
lower threshold, then R
becomes parallel with R
for the
upper threshold. Note that the application requires rail-to-rail
input as well.
The resistor values shown in
Figure 6
are the closest prac-
tical to calculated values.
Fast Start-up
The LP3982 provides fast start-up time for better system
efficiency. The start-up speed is maintained when using the
optional noise bypass capacitor. An internal 500μA current
source charges the capacitor until it reaches about 90% of its
final value.
20036921
FIGURE 5. Power on Delayed Reset Application
20036902
FIGURE 6. Minimum Battery Detector that Disconnects
the Load Via the SHDN Pin of the LP3982
L
www.national.com
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LP3982ILD33/NOPB | 制造商:Texas Instruments 功能描述: |
| LP3982ILD-ADJ | 功能描述:低壓差穩壓器 - LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節:0.3 % 輸出端數量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| LP3982ILD-ADJ/NOPB | 功能描述:低壓差穩壓器 - LDO MICROPWR ULT LDO LW- NO 300MA CMOS REG RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節:0.3 % 輸出端數量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| LP3982ILD-AJD | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Micropower, Ultra Low-Dropout, Low-Noise, 300mA CMOS Regulator |
| LP3982ILDX-1.8 | 功能描述:低壓差穩壓器 - LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節:0.3 % 輸出端數量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
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