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參數資料
| 型號： | LP62S16128V-70LLT |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 128K的× 16位低電壓CMOS的SRAM |
| 文件頁數： | 1/14頁 |
| 文件大小： | 160K |
| 代理商： | LP62S16128V-70LLT |
LP62S16128B-I Series
128K X 16 BIT LOW VOLTAGE CMOS SRAM
(August, 2001, Version 1.0)
1
AMIC Technology, Inc.
Features
n Operating voltage: 2.7V to 3.6V
n Access times: 55/70 ns (max.)
n Current:
Very low power version: Operating: 55ns 40mA (max.)
70ns 35mA (max.)
Standby:
10
A (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 44-pin TSOP and 48-ball CSP (6 x 8 mm)
packages
General Description
The LP62S16128B-I is a low operating current 2,097,152-
bit static random access memory organized as 131,072
words by 16 bits and operates on low power voltage from
2.7V to 3.6V. It is built using AMIC's high performance
CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
n
n TSOP
n
n CSP (Chip Size Package)
48-pin Top View
I/O9
I/O10
GND
VCC
I/O15
I/O16
NC
A8
NC
A9
A12
A10
A11
NC
A13
A14
A15
I/O8
I/O7
I/O3
I/O1
GND
VCC
A0
A3
A5
A6
A4
A1
A2
NC
6
5
4
3
2
1
A
B
C
D
E
F
G
H
I/O14
I/O13
I/O12
I/O11
NC
A7
A16
I/O2
I/O4
I/O5
I/O6
LB
HB
WE
OE
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
GND
I/O5
I/O6
I/O7
I/O8
WE
A16
A15
A14
A13
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A11
A10
A9
A8
NC
I/O9
I/O10
I/O11
I/O12
VCC
GND
I/O13
I/O14
I/O15
I/O16
LB
HB
OE
A7
A6
LP62S16128BV-I
A12
A5
A4
NC
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