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參數資料
| 型號： | LS7211-S |
| 英文描述： | Delay Line |
| 中文描述： | 延遲線 |
| 文件頁數： | 1/8頁 |
| 文件大?。?/td> | 66K |
| 代理商： | LS7211-S |
PROGRAMMABLE DIGITAL DELAY TIMER
DESCRIPTION:
The LS7211/LS7212 are monolithic CMOS integrated cir-
cuits for generating digitally programmable delays. The de-
lay is controlled by 8 binary weighted inputs, WB0-WB7, in
conjunction with an applied clock or oscillator frequency.
The programmed time delay manifests itself in the Delay
Output (OUT) as a function of the Operating Mode selected
by the Mode Select inputs A and B: One-Shot, Delayed
Operate, Delayed Release or Dual Delay. The time delay is
initiated by a transition of the Trigger Input (TRIG).
I/O DESCRIPTION:
MODE SELECT Inputs (A &B, Pins 1 & 2)
The 4 operating modes are selected by Inputs A and B
according to Table 1
TABLE 1. MODE SELECTION
A
0
0
1
1
B
0
1
0
1
MODE
One-Shot (OS)
Delayed Operate (DO)
Delayed Release (DR)
Dual Delay (DD)
Each input has an internal pull-up resistor of about 500K
.
One-Shot Mode (OS)
A positive transition at the TRIG input causes OUT to
switch low without delay and starts the delay timer. At the
end of the programmed delay timeout, OUT switches high.
If a delay timeout is in progress when a positive transition
occurs at the TRIG input, the delay timer will be restarted.
A negative transition at the TRIG input has no effect.
Delayed Operate Mode (DO)
A positive transition at the TRIG input starts the delay tim-
er. At the end of the delay timeout, OUT switches low. A
negative transition at the TRIG input causes OUT to switch
high without delay. OUT is high when TRIG is low.
Delayed Release Mode (DR)
A negative transition at the TRIG input starts the delay tim-
er. At the end of the delay timeout, OUT switches high. A
postive transition at the TRIG input causes OUT to switch
low without delay. OUT is low when TRIG is high.
Dual Delay Mode (DD)
A positive or negative transition at the TRIG input starts
the delay timer. At the end of the delay timeout, OUT
switches to the logic state which is the inverse of the TRIG
input. If a delay timeout is in progress when a transition
occurs at the TRIG input, the delay timer is restarted.
7211-041700-1
FEATURES:
8-bit programmable delay from nanoseconds to days
On chip oscillator (RC or Crystal) or external clock time base
Selectable prescaler for real time delay generation based
on 50Hz/60Hz time base or 32.768KHz watch crystal
Four operating modes
Reset input for delay abort
Low quiescent and operating current
Direct relay drive
+4V to +18V operation (V
DD
-V
SS
)
LS7211/LS7212 (DIP), LS7211-S/LS7212-S (SOIC)-See Figure 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
L
L
OUT
V
DD
(+V)
A
B
TRIG
RC/CLOCK
RCS/CLKS
PSCLS
RESET
V
SS
(-V)
WB0
WB1
WB2
WB3
WB4
WB5
WB6
WB7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
L
L
OUT
V
DD
(+V)
A
B
TRIG
XTLI/CLOCK
XTLO
PSCLS
RESET
V
SS
(-V)
WB0
WB1
WB2
WB3
WB4
WB5
WB6
WB7
FIGURE 1
PIN ASSIGNMENT - TOP VIEW
June 1997
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
LS7211-7212
UL
A3800
相關PDF資料 |
PDF描述 |
|---|---|
| LS7212-S | Delay Line |
| LSA1504 | ASIC |
| LSA1501 | ASIC |
| LSA1502 | ASIC |
| LSA1503 | ASIC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LS7212 | 制造商:LSI 制造商全稱:LSI 功能描述:PROGRAMMABLE DIGITAL DELAY TIMER |
| LS7212N | 制造商:LSI 制造商全稱:LSI 功能描述:PROGRAMMABLE DIGITAL DELAY TIMER |
| LS7212-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| LS7213 | 制造商:LSI 制造商全稱:LSI 功能描述:PROGRAMMABLE DIGITAL DELAY TIMER |
| LS7213R | 制造商:LSI 制造商全稱:LSI 功能描述:PROGRAMMABLE DIGITAL DELAY TIMER |
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