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參數資料
型號: LT1248IS#PBF
廠商: Linear Technology
文件頁數: 7/12頁
文件大小: 164K
描述: IC PFC CTRLR AVERAGE CURR 16SOIC
標準包裝: 50
模式: 平均電流
頻率 - 開關: 300kHz
電流 - 啟動: 250µA
電源電壓: 15.5 V ~ 27 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 16-SOIC
包裝: 管件
產品目錄頁面: 1338 (CN2011-ZH PDF)
7
LT1248
PI FU CTIO S
U
U
U
Pin 12 (R
SET
): A resistor from R
SET
 to GND sets the
oscillator charging current and the maximum multiplier
output current which is used to limit the maximum line
current.
I
M(MAX)
 = 3.75V/R
SET
Pin 13 (SS): Soft-Start. When either V
CC
 or EN/SYNC goes
low, the SS pin will stay at 0V. With a capacitor from the
pin to GND, the 12礎 charging current slowly brings up the
SS to 8V; below 7.5V SS is the reference input to the
voltage amplifier. At supply dropout or EN/SYNC low, the
soft start capacitor will be quickly discharged.
Pin 14 (C
SET
):  The capacitor from this pin to GND, and
R
SET
, determine oscillator frequency. The oscillator ramp
is 5V, and the frequency = 1.5/(R
SET
 " C
SET
).
Pin 15 (V
CC
): This is the supply for the chip. The LT1248
has a very fast gate driver required to fast charge high
power MOSFET gate capacitance. High current spikes
occur during charging. For good supply bypass, a 0.1礔
ceramic capacitor in parallel with a low ESR electrolytic
capacitor, 56礔 or higher is required in close proximity to
IC GND.
Pin 16 (GTDR): The MOSFET gate driver is a 1.5A fast
totem pole output. It is clamped at 15V, but capacitive
loads like MOSFET gates may cause overshoot. A gate
series resistor of at least 5& will prevent the overshoot.
I
AC
 (礎)
0
300
150
0
1248 G04
250
500
VA
OUT
 = 7V
VA
OUT
 = 6.5V
VA
OUT
 = 6V
VA
OUT
 = 5.5V
VA
OUT
 = 5V
VA
OUT
 = 4.5V
VA
OUT
 = 4V
VA
OUT
 = 3.5V
VA
OUT
 = 3V
VA
OUT
 = 2.5V
Figure 1. Multiplier Current I
M
 vs I
AC
 and VA
OUT
S
A
PPLICATI
U
U
I FOR  ATIO
Multiplier
The multiplier is a current multiplier with high noise
immunity in a high power switching environment. The
current gain is: I
M
 = (I
AC
 " I
EA
2
)/(200礎)
2
, with I
EA
 = (VA
OUT
 2V)/25k. With a square function, because of the lower
gain at light power load, system stability is maintained and
line current distortion caused by the line frequency AC
Error Amplifier
The error amplifier has a 100dB DC gain and 3MHz unity-
gain frequency. The output is internally clamped at 13.5V.
The noninverting input is tied to the 7.5V V
REF
 through a
diode and can be pulled down from the SS (soft-start) pin.
Current Amplifier
The current amplifier has a 110dB DC gain, 3MHz unity-
gain frequency, and a 2V/祍 slew rate. It is internally
clamped at 8.5V. Note that in the current averaging opera-
tion, high gain at twice the line frequency is necessary to
minimize line current distortion. Because CA
OUT
 may need
to swing 5V over one line cycle at high line condition,
14mV AC will be needed at the inputs of the current
amplifier for a gain of 350 at 120Hz. Especially at light load
when the current loop reference signal is small, lower gain
will distort the reference signal and line current. If signal
gain at switching frequency is too high, the system be-
haves more like a current mode system and can cause
subharmonic oscillation. Therefore, the current amplifier
should be compensated to have a gain of less than 15 at
the switching frequency, but more than 250 at twice the
line frequency.
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