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參數資料
| 型號： | LT3150CGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數： | 16/20頁 |
| 文件大小： | 259K |
| 描述： | IC REG CTRLR SGL POS ADJ 16-SSOP |
| 產品培訓模塊： | More Information on LDOs |
| 標準包裝： | 2,500 |
| 類型： | 正，可調式 |
| 輸出數： | 1 |
| 輸出電壓： | 2.5 V ~ 18.4 V |
| 電流 - 電源： | 12mA |
| 輸入電壓： | 1.5 V ~ 10 V，10 V ~ 20 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
16
LT3150
3150f
APPLICATIO S I FOR ATIO
U
U
U
Figure 4. Typical Bode Plot for
Low ESR Ceramic Output Capacitors
FREQUENCY (Hz)
P2 IS A FUNCTION
OF LOAD CURRENT
I
LOAD(MIN)
MANY HIGH ORDER POLES AND
ZEROS PAST UNITY-GAIN f
X
I
LOAD(MAX)
3150 F04
AV1 = g
m1
" R1 " (V
REF
/V
OUT
)
AVOL = g
m1
" R
O
" (V
REF
/V
OUT
)
P2 = g
m
(Q1)/(2 " ?" C
O
)
Z1 = 1/(2 " ?" R1 " C1)
P1 = 1/(2 " ?" R
O
" C1)
V
REF
V
OUT
f
X
= g
m1
" R1 "
"
g
m
(Q1)
2 " ?" C
O
FREQUENCY (Hz)
P2 IS A FUNCTION
OF LOAD CURRENT
I
LOAD(MIN)
MANY HIGH ORDER POLES AND
ZEROS PAST UNITY-GAIN f
X
I
LOAD(MAX)
3150 F05
AV1 = AVOL " (P1/P2)
= (g
m1
" C
O
)/(g
m
(Q1) " C1)
AVOL = g
m1
" R
O
" (V
REF
/V
OUT
)
P2 = g
m
(Q1)/(2 " ?" C
O
)
Z1 = 1/(2 " ?" ESR " C
O
)
P1 = 1/(2 " ?" R
O
" C1)
f
X
=
g
m1
2 " ?" C1
Figure 5. Typical Bode Plot for Tantalum
or Electrolytic Output Capacitors
higher unity gain bandwidth crossover frequency, f
X
. f
X
must be set to a value that provides adequate phase and
gain margin and this criteria limits the shelf gain value. If
higher shelf gain is required for a given application, then
increase output capacitance.
In both output capacitor cases, the location of the second
pole, P2, is set by the MOSFETs transconductance, g
m
(Q1),
and the value of the output capacitor, C
O
. The output load
current sets the transconductance of the MOSFET. P2
moves as a function of load current and consequently, so
does the unity-gain crossover frequency, f
X
. Figures 4 and
5 depict this behavior. At very low output currents, P2s
location moves to a very low frequency. Therefore, set Z1
at a low enough frequency to provide adequate phase boost.
A temptation is to set Z1s value equal to P2s value at
minimum output load current. The bode plot then exhibits
a single pole response at minimum output current. How-
ever, this either makes the shelf gain and f
X
too high for
stability or it makes the small signal settling time very long.
Set Z1 above the minimum value for P2 so that at small
output load currents, the second pole P2 occurs and then
Z1 provides phase boost prior to crossing unity gain.
At the highest load current levels, several poles and zeros
exist just beyond the unity-gain crossover frequency.
Sometimes, the gain peaks back above unity and a high
frequency, low level oscillation appears. A high frequency
pole is necessary to roll off the response. In the case of
ceramic output capacitors, capacitor C2 in Figure 4 sets
this pole in combination with R1. In the case of electrolytic
or tantalum output capacitors, some small ceramic ca-
pacitors in parallel with the main output capacitors usually
provide the desired response.
Finally, look for very high frequency gate oscillations in the
range of 2MHz to 10MHz. Small MOSFETs with low gate
capacitance are most susceptible to this issue. This oscil-
lation is typically caused by the MOSFETs effective gate
capacitance and the MOSFETs parasitic source induc-
tance resonating. The MOSFETs source inductance is the
sum of the devices bond wire plus package lead induc-
tance and the PCB trace inductance between the MOSFETs
source and the actual output capacitors. Although the
MOSFETs internal inductance is fixed, proper PCB layout
techniques minimize the external inductance. Minimize
the distance between the MOSFETs source and the output
decoupling capacitors and run wide planes if possible.
Connect the top of the feedback divider at the point closest
to the actual load rather than the MOSFET source. If high
frequency oscillations persist, a small value resistor in the
range of 1& to 50& in series with the gate of the MOSFET
typically eliminates this ringing. The inclusion of a gate
resistor may permit the high frequency pole discussed in
the preceding paragraph to be eliminated or fine tuned.
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