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參數資料
| 型號： | LTC1064-7CSW#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數： | 1/16頁 |
| 文件大小： | 0K |
| 描述： | IC FILTR 8TH ORDR LOWPASS 16SOIC |
| 標準包裝： | 1,000 |
| 濾波器類型： | 線性相位，低通開關電容器 |
| 頻率 - 截止或中心： | 100kHz |
| 濾波器數： | 1 |
| 濾波器階數： | 8th |
| 電源電壓： | ±2.37 V ~ 8 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
1
LTC1064-7
10647fb
Linear Phase, 8th Order
Lowpass Filter
■ Steeper Roll-Off Than 8th Order Bessel Filters
■ fCUTOFF up to 100kHz
■
Phase Equalized Filter in 14-Pin Package
■ Phase and Group Delay Response Fully Tested
■ Transient Response Exhibits 5% Overshoot and
No Ringing
■ Wide Dynamic Range
■ 72dB THD or Better Throughout a 50kHz Passband
■
No External Components Needed
■ Available in 14-Pin DIP and 16-Pin SO Wide
Packages
The LTC
1064-7 is a clock-tunable monolithic 8th order
lowpass filter with linear passband phase and flat group
delay. The amplitude response approximates a maximally
flat passband while it exhibits steeper roll-off than an
equivalent 8th order Bessel filter. For instance, at twice the
cutoff frequency the filter attains 34dB attenuation (vs
12dB for Bessel), while at three times the cutoff frequency,
the filter attains 68dB attenuation (vs 30dB for Bessel).
The cutoff frequency of the LTC1064-7 is tuned via an
external TTL or CMOS clock.
The LTC1064-7 features wide dynamic range. With single
5V supply, the S/N + THD is 76dB. Optimum 92dB S/N is
obtained with
±7.5V supplies.
The clock-to-cutoff frequency ratio of the LTC1064-7 can
be set to 50:1 (Pin 10 to V+) or 100:1 (Pin 10 to V –).
When the filter operates at clock-to-cutoff frequency ratio
of 50:1, the input is double-sampled to lower the risk of
aliasing.
The LTC1064-7 is pin-compatible with the LTC1064-X
series, LTC1164-7 and LTC1264-7.
■ Data Communication Filters
■ Time Delay Networks
■ Phase-Matched Filters
80kHz Linear Phase Lowpass Filter
Eye Diagram
1
2
3
4
5
6
7
14
13
12
11
10
9
8
LTC1064-7
VIN
7.5V
–7.5V
CLK = 4MHz
7.5V
VOUT
NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A
0.1
F CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED
CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE
OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT
PIN AND THE fCLK LINE.
1064-7 TA01
1V/DIV
1064-7 TA02
1
s/DIV
VS = ±7.5V
fCLK = 4MHz
RATIO = 50:1
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
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