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| 型號(hào)： | LTC4224IDDB-2#TRPBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大小： | 220K |
| 描述： | IC CNTRLR HOT SWAP DUAL 10-DFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 1 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN-EP（3x2） |
| 包裝： | 帶卷 (TR) |
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LTC4224-1/LTC4224-2
11
422412fa
APPLICATIONS INFORMATION
Figure 11. Recommended Layout for Input
Supply Transient Protection Network
422412 F11
R
SNUB
C
SNUB
LTC4224
1
V
CC2
GATE2
GND
2
SENSE2
3
4
5
10
9
8
7
6
Z1
V
CC2
SNUBBER
NETWORK
VIAS TO
GND PLANE
PCB layout for the sense resistors and the power MOSFETs
should include good thermal management techniques for
optimal device power dissipation. A recommended PCB
layout for the sense resistors and the power MOSFET
around the LTC4224 is illustrated in Figure 12. Note that
it is important to keep the trace from the LTC4224s GATE
pin to the FDS6911s gate short.
In Hot Swap applications where load currents can be 10A,
wide PCB traces are recommended to minimize resistance
and temperature rise. The suggested trace width for 1oz
copper foil is 0.03" for each ampere of DC current to keep
PCB trace resistance, voltage drop and temperature rise to
a minimum. Note that the sheet resistance of 1oz copper
foil is approximately 0.5m?square and voltage drops
due to trace resistances add up quickly in high current
applications.
In most applications, it is necessary to use plated-through
vias to make circuit connections from component layers to
power and ground layers internal to the PCB. For 1oz cop-
per foil plating, a general rule is 1A of DC current per via.
Consult your PCB fabrication facility for design rules
pertaining to other plating thicknesses.
Design Example
As a design example, consider the following speci cations:
V
CC1
= 5V , V
CC2
= 3.3V , I
LOAD1(MAX)
= 1A, I
LOAD2(MAX)
= 2A,
C
LOAD1
= C
LOAD2
= 150糉 (see Figure 1).
First, select the sense resistor for each supply. Calculate
the R1 and R2 values based on the maximum load cur-
rent and the minimum circuit breaker threshold limit,
擵
SENSE(CB)(MIN)
.
If a 1% tolerance is assumed for the sense resistors, then
the following values of resistance should suf ce:
Table 2. Sense Resistor Values
SUPPLY VOLTAGE
R
SENSE
(1%)
I
TRIP(MIN)
I
TRIP(MAX)
5V
15m?/DIV>
1.49A
1.85A
3.3V
10m?/DIV>
2.23A
2.78A
For proper operation, I
TRIP(MIN)
must exceed the maxi-
mum load current with margin, so R
SENSE1
= 15m?and
R
SENSE2
= 10m?should suf ce for the V
CC1
and V
CC2
supplies respectively.
Figure 12. Recommended Layout for
Power MOSFET and Sense Resistors
422412 F12
TOP SIDE
FDS6911
BOTTOM SIDE
LTC4224
11
6
8
7
9
10
5
4
2
3
1
3
1
5V
3.3V
R2
R1
Also, bypass locally with a 10糉 electrolytic and 100nF
ceramic, or alternatively clamp the input with a transient
voltage suppressor (Z1) as shown in Figure 10. A 10?
100nF snubber damps the response and eliminates ring-
ing. A recommended layout of the transient protection
devices Z1, R
SNUB
and C
SNUB
around the LTC4224 is
shown in Figure 11.
PCB Layout Considerations
For proper operation of the LTC4224s electronic circuit
breaker, Kelvin connections to the sense resistors are
strongly recommended. The PCB layout should be balanced
and symmetrical to minimize wiring errors. In addition, the
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