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參數資料
| 型號： | LTC4251-2CS6#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數： | 12/24頁 |
| 文件大小： | 266K |
| 描述： | IC CTRLR HOTSWAP NEGVOLT SOT23-6 |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | -43V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 細型，TSOT-23-6 |
| 供應商設備封裝： | SOT-23-6 |
| 包裝： | 帶卷 (TR) |
12
425112fd
LTC4251/LTC4251-1/
LTC4251-2
For more information www.linear.com/4251
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load,
but it will not reset the circuit breaker latch. Returning the
supply voltage to an acceptable range restarts the GATE
pin provided all interlock conditions except TIMER are met.
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor, C
T
, is used
at TIMER to provide timing for the LTC4251/LTC4251-1/
LTC4251-2. Four different charging and discharging modes
are available at TIMER:
1. 5.8礎 slow charge; initial timing delay
2. 230礎 fast charge; circuit breaker delay
3. 5.8礎 slow discharge; circuit breaker cool-off
4. Low impedance switch; resets capacitor after initial
timing delay, in undervoltage lockout, and in overvoltage
For initial startup, the 5.8礎 pull-up is used. The low im-
pedance switch is turned off and the 5.8礎 current source
is enabled when the four interlock conditions are met. C
T
charges to 4V in a time period given by:
t =
4V " C
T
5.8礎
(1)
When C
T
reaches 4V (V
TMRH
), the low impedance switch
turns on and discharges C
T
. The GATE output is enabled
and the load turns on.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than 50mV across R
S
,
the TIMER pin charges C
T
with 230礎. If C
T
charges to
4V , the GATE pin pulls low and the LTC4251/LTC4251-1/
LTC4251-2 latch off. The part remains latched off until
either the UV/OV pin is momentarily pulsed low, or V
IN
dips into UVLO and is then restored. The circuit breaker
timeout period is given by
t =
4V " C
T
230礎
(2)
Intermittent overloads may exceed the 50mV threshold
at SENSE, but if their duration is sufficiently short TIMER
will not reach 4V and the LTC4251/LTC4251-1/LTC4251-2
will not latch off. To handle this situation, the TIMER
discharges C
T
slowly with a 5.8礎 pull-down whenever
the SENSE voltage is less than 50mV . Therefore any in-
termittent overload with an aggregate duty cycle of 2.5%
or more will eventually trip the circuit breaker and latch
off the LTC4251/LTC4251-1/LTC4251-2. Figure 3 shows
the circuit breaker response time in seconds normalized
to 1礔 . The asymmetric charging and discharging of C
T
is
a fair gauge of MOSFET heating.
APPLICATIONS INFORMATION
GATE
GATE is pulled low to V
EE
under any of the following
conditions: in UVLO, during the initial timing cycle, in an
overvoltage condition, or when the LTC4251/LTC4251-1/
LTC4251-2 are latched off after a short-circuit. When GATE
turns on, a 58礎 current source charges the MOSFET gate
and any associated external capacitance. V
IN
limits gate
drive to no more than 14.5V .
Gate-drain capacitance (C
GD
) feed through at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET . A unique circuit
pulls GATE low with practically no usable voltage at V
IN
,
and eliminates current spikes at insertion. A large external
gate-source capacitor is thus unnecessary for the purpose
of compensating C
GD
. Instead, a smaller value (e10nF)
capacitor C
C
is adequate. C
C
also provides compensation
for the analog current limit loop.
Figure 3. Circuit Breaker Response Time
FAULT DUTY CYCLE, D (%)
20
40
60
80
0
10
1
0.1
0.01
100
425112 F03
t
C
T
(礔)
4
(235.8 " D) 5.8
=
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