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參數資料
| 型號： | LUC4AU01 |
| 廠商： | Lineage Power |
| 英文描述： | ATM Layer UNI Manager (ALM)(ATM 層UNI管理器(ALM)) |
| 中文描述： | ATM層統一管理（ALM）的（自動柜員機層統一管理器（簡稱ALM）） |
| 文件頁數： | 1/6頁 |
| 文件大小： | 164K |
| 代理商： | LUC4AU01 |
Preliminary Product Brief
March 1997
LUC4AU01
ATM Layer UNI Manager (ALM)
S
LUCENT TECHNOLOGIES—PROPRIETARY
Use pursuant to Company Instructions
Introduction
The ALM IC is part of the ATLANTA chip set consist-
ing of four devices that provide a highly integrated,
innovative, and complete VLSI solution for implement-
ing the ATM layer core of an ATM switch system. The
chip set enables construction of high-performance,
feature-rich, and cost-effective ATM switches, scal-
able over a wide range of switching capacities. This
document discusses the ALM device.
Features
I
Performs ATM layer User- or Network-Network Inter-
face (UNI or NNI) management functions, supporting
up to 662 Mbits/s of ATM traffic (full duplex).
I
Controls up to 30 full-duplex ports through
MultiPHY (MPHY) devices on the physical layer side.
— Manages virtual connection (VC) and virtual path
(VP) parameter table in external memory.
— Any port can be configured as a UNI or NNI.
— Performs VPI/VCI translation for each connection
on egress while allowing reusability of same VPI/
VCI on different UNIs.
— Optionally performs the ATM Forum compliant
Dual Leaky-Bucket Policing, with configurable
parameters per connection, enabled on a global
or per VP basis.
— Facilitates call set up and tear down through VC
parameter table update via microprocessor port.
— Optionally translates or passes the generic flow
control (GFC) field of the egress ATM cell header
for NNI or UNI applications.
I
Supports up to 64K VCs on ingress and up to 64K
VCs on egress with scalable external memory.
I
Maintains variety of optional per-connection 31-bit
statistics counters in external memory:
— Ingress CLP0s, ingress CLP1s, nonconforming
leaky-bucket A, and nonconforming leaky-bucket
B or
— Ingress conforming CLP0s, conforming CLP1s,
nonconforming CLP0s, and nonconforming
CLP1s.
— Egress CLP0s, and egress CLP1s.
I
Provides UTOPIA Level II interface on the physical
layer side, and UTOPIA Level II Plus interface to the
ATM layer (or switch core) side.
I
Provides two modes of operation:
— In user-specific proprietary mode, prepends
user-programmable local routing header (up to
12 bytes) to ATM cells on ingress.
— In ATLANTA-compatible mode, prepends a pre-
formatted header (required by the ATLANTA chip
set) to ATM cells on ingress.
I
Supports multicasting to 30 different MPHY ports on
egress by providing independent VPI/VCI transla-
tion.
I
Provides a generic, Intel* or Motorola
compatible,
16-bit microprocessor interface with interrupt.
I
Optionally captures ABR RM, F4, and F5 OA&M
cells on ingress and any VC on egress to micropro-
cessor port interface.
I
Supports read and write modes for cell extraction
and insertion via the microprocessor interface.
I
Supports 32-bit wide external memory interface
using synchronous SRAMs (with 20 ns cycle time).
I
Includes system diagnostic features:
— Parity on the UTOPIA II interface, UTOPIA II Plus
interface, and external memory interface.
— Egress to ingress loopback.
— Cell insertion via microprocessor port capabili-
ties.
I
Facilitates circuit board testing with on-chip IEEE
standard boundary scan
I
Fabricated as a low-power, monolithic IC in 0.5
μ
m,
3.3 V CMOS technology, with 5 V-tolerant and TTL-
level compatible I/O.
I
Available in a thermally enhanced 240-pin SQFP
package.
*
Intel
Motorola
IEEE
Electronics Engineers, Inc.
is a registered trademark of Intel Corporation.
is a registered trademark of Motorola, Inc.
is a registered trademark of The Institute of Electrical and
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LUC4AU01SC5DB | 制造商:LUCENT 功能描述:* |
| LUC4AU01-SC5-DB | 制造商:Agere Systems 功能描述: |
| LUC4AU01-SC6 | 制造商:Alcatel-Lucent 功能描述: 制造商:LUCENT 功能描述: |
| LUC4AU01-SC6-DB | 制造商:Alcatel-Lucent 功能描述:Electronic Component |
| LUC4AV01-SC6 | 制造商:Alcatel-Lucent 功能描述: 制造商:LUCENT 功能描述: |
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