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參數資料
| 型號： | LUCL9218GAR-DT |
| 英文描述： | CAT5E PATCH CABLES SNAGLESS,BLUE 100 FT |
| 中文描述： | 低成本線接口 |
| 文件頁數： | 1/30頁 |
| 文件大小： | 378K |
| 代理商： | LUCL9218GAR-DT |
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Data Sheet
November 2001
L9218A/G Low-Cost Line Interface
Features
I
Basic forward battery only SLIC functionality at a
low cost
I
Pin compatible with Agere Systems Inc. L9219 and
L9217 SLIC
I
Low active power (typical 138 mW during on-hook
transmission)
I
Low-power scan mode for low-power, on-hook
power dissipation (59 mW typical)
I
Minimal external components
I
Distortion-free, on-hook transmission
I
Convenient operating states:
— Forward battery low current limit
— Forward battery high current limit
— Low-power scan
— Disconnect (high impedance)
I
Adjustable supervision functions:
— Off-hook detector with hysteresis
— Ring trip detector
I
Logic controlled high and low current limit
I
Two gain options to optimize the codec interface
I
Thermal protection with thermal shutdown indica-
tion
Description
This general-purpose electronic subscriber loop
interface circuit (SLIC) is optimized for low cost, while
still providing a satisfactory set of features.
The L9218 is pin-for-pin compatible with the Agere
L9219 and L9217 SLICs.
The L9218 requires a 5 V power supply and single
battery to operate. This is a forward battery only
device. Additionally, a low-power scan mode,
wherein all circuitry except the off-hook supervision is
shut down to conserve power, is available.
Via the logic inputs, a low or high current limit may be
selected. The low value is set via a single external
resistor, and the high value is 1.4 times the low value.
Device overhead is fixed and is adequate for
3.14 dBm into 900
of on-hook transmission.
Both the loop supervision and ring trip supervision
functions are offered with user-controlled thresholds
via external resistors.
The L9218 is offered with a receive gain that is opti-
mized for interface to a first-generation type codec
(L9218A). It is also offered with a gain option that is
optimized for interface to a third- or fourth-generation
type codec (L9218G). In both cases, minimizing
external components required at this interface. In the
receive direction, the device may be dc-coupled to a
third-generation codec. No dc blocking capacitors
are needed.
Data control is via a parallel data control scheme.
The device is available in a 28-pin PLCC package. It
is built by using a 90 V complementary bipolar
(CBIC) process.
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