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參數(shù)資料
| 型號： | LUCW3011FCL |
| 英文描述： | 1 GHz Quadrature Modulator |
| 中文描述： | 1 GHz的正交調(diào)制器 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 199K |
| 代理商： | LUCW3011FCL |
W3011
1 GHz Quadrature Modulator
Data Sheet
September 1999
Features
+
Guaranteed performance at 2.7 V power supply
+
Output power of 3 dBm into 50
load (single-
ended) with 3 V operation
+
Direct RF modulation with or without offset mixer
+
Automatic power control (APC) capability
+
Accurate 90° phase shifter for carrier
+
Double-balanced active mixers minimize carrier
feedthrough (origin offset)
+
Low-current sleep mode
Applications
+
PDC 800 and American digital cellular mobile
terminals
+
Cellular base stations
Description
The W3011 1 GHz Quadrature Modulator is a
monolithic integrated circuit that provides direct
modulation of an RF carrier by I & Q baseband
inputs. It is particularly suited for use in mobile and
handheld cellular telephones designed to the IS-136
(North American 824 MHz to 849 MHz), PDC
(Japan RCR-STD27 889 MHz to 958 MHz), and
other digital personal-communications standards.
The circuit block diagram is shown in Figure 1. From
two LO signals, LOL and LOH, the offset mixer
produces an internal LO signal, which prevents the
external VCOs from being pulled by the large
transmitted signal. The phase shifter splits the LO
signal into two carriers with 90° phase separation
and equal amplitude.
These signals are fed to the in-phase (I) and
quadrature-phase (Q) double-balanced mixers. The
resulting signals are summed and fed into the output
amplifier. This amplifier can provide 0 dBm linear
output power, minimum, into a 50
load.
The output power can be attenuated up to 50 dB by
applying a control voltage to the APC input.
Nominally, the output power is at maximum
(+3 dBm) with V
APC
> 2.2 V, and at minimum
(–50 dBm) with V
APC
< 0.8 V.
A CMOS/TTL-compatible logic input allows the
device to be put into a powerdown mode in which
less than 10 μA of supply current is consumed.
BIAS AND CONTROL
V
CC
ENABLE
GROUND
∑
φ
EXTERNAL FILTER
OR
DIRECT LO INPUT
APC
RF
OUT
–
π
/4
+π
/4
Q
I
LOL IN
50
LOH IN
50
Figure 1. Circuit Block Diagram
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