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參數資料
| 型號： | LV8573AM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | LV8573A Low Voltage Real Time Clock (RTC) |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
| 封裝： | PLASTIC, SOIC-24 |
| 文件頁數： | 4/18頁 |
| 文件大小： | 306K |
| 代理商： | LV8573AM |
Timing Waveforms
Read Timing Diagram
TL/F/11418–3
Write Timing Diagram
TL/F/11418–4
Pin Description
CS, RD, WR (Inputs):
These pins interface to
m
P control
lines. The CS pin is an active low enable for the read and
write operations. Read and Write pins are also active low
and enable reading or writing to the RTC. All three pins are
disabled when power failure is detected. However, if a read
or write is in progress at this time, it will be allowed to com-
plete its cycle.
A0–A4 (Inputs):
These 5 pins are for register selection.
They individually control which location is to be accessed.
These inputs are disabled when power failure is detected.
OSC IN (Input): OSC OUT (Output):
These two pins are
used to connect the crystal to the internal parallel resonant
oscillator. The oscillator is always running when power is
applied to V
BB
and V
CC
.
MFO (Output):
The multi-function output can be used as a
second interrupt (Power fail) output for interrupting the
m
P.
This pin can also provide an output for the oscillator. The
MFO output is configured as push-pull, active high for nor-
mal or single power supply operation and as an open drain
during standby mode (V
BB
l
V
CC
). If in battery backed
mode and a pull-up resistor is attached, it should be con-
nected to a voltage no greater than V
BB
.
INTR (Output):
The interrupt output is used to interrupt the
processor when a timing event or power fail has occurred
and the respective interrupt has been enabled. The INTR
output is permanently configured active low, open drain. If in
battery backed mode and a pull-up resistor is attached, it
should be connected to a voltage no greater than V
BB
.
D0–D7 (Input/Output):
These 8 bidirectional pins connect
to the host
m
P’s data bus and are used to read from and
write to the RTC. When the PFAIL pin goes low and a write
is not in progress, these pins are at TRI-STATE.
PFAIL (Input):
In battery backed mode, this pin can have a
digital signal applied to it via some external power detection
logic. When PFAIL
e
logic 0 the RTC goes into a lockout
mode, in a minimum of 30
m
s or a maximum of 63
m
s unless
lockout delay is programmed. In the single power supply
mode, this pin is not useable as an input and should be tied
to V
CC
. Refer to section on Power Fail Functional Descrip-
tion.
V
BB
(Battery Power Pin):
This pin is connected to a back-
up power supply. This power supply is switched to the inter-
nal circuitry when the V
CC
becomes lower than V
BB
. Utiliz-
ing this pin eliminates the need for external logic to switch in
and out the back-up power supply. If this feature is not to be
used then this pin must be tied to ground, the RTC pro-
grammed for single power supply only, and power applied to
the V
CC
pin.
V
CC
:
This is the main system power pin.
GND:
This is the common ground power pin for both V
BB
and V
CC
.
4
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