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參數資料
| 型號： | LV8573AN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | LV8573A Low Voltage Real Time Clock (RTC) |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數： | 10/18頁 |
| 文件大小： | 306K |
| 代理商： | LV8573AN |
Functional Description
(Continued)
ternal interrupt will be issued. Note that the linear power fail
circuitry is switched off automatically when using V
BB
in
standby mode.
INITIAL POWER ON DETECT AND
POWER FAIL TIME SAVE
There are two other functions provided on the LV8573A to
ease power supply control. These are an initial Power On
detect circuit, which also can be used as a time keeping
failure detect, and a time save on power failure.
On initial power up the Oscillator Fail Flag will be set to a
one and the real time clock start bit reset to a zero. This
indicates that an oscillator fail event has occurred, and time
keeping has failed.
The Oscillator Fail flag will not be reset until the real-time
clock is started. This allows the system to discriminate be-
tween an initial power-up and recovery from a power failure.
If the battery backed mode is selected, then bit D6 of the
Periodic Flag Register must be written low. This will not af-
fect the contents of the Oscillator Fail Flag.
To relieve CPU overhead for saving time upon power failure,
the Time Save Enable bit is provided to do this automatical-
ly. (See also Reading the Clock: Latched Read.) The Time
Save Enable bit, when set, causes the Time Save RAM to
follow the contents of the clock. This bit can be reset by
software, but if set before a power failure occurs, it will auto-
matically be reset when the clock switches to the battery
supply (not when a power failure is detected by the PFAIL
pin). Thus, writing a one to the Time Save bit enables both a
software write or power fail write.
SINGLE POWER SUPPLY APPLICATIONS
The LV8573A can be used in a single power supply applica-
tion. To achieve this, the V
BB
pin must be connected to
ground, and the power connected to V
CC
. The Oscillator
Failed/Single Supply bit in the Periodic Flag Register should
be set to a logic 1, which will disable the oscillator battery
reference circuit. The power fail interrupt should also be dis-
abled. This will turn off the linear power fail detection cir-
cuits, and will eliminate any quiescent power drawn through
these circuits.
DETAILED REGISTER DESCRIPTION
There are 5 external address bits: Thus, the host microproc-
essor has access to 28 locations at one time. An internal
switching scheme provides a total of 30 locations.
The only register that does not get switched is the Main
Status Register. It contains the register select bit as well as
status information.
A memory map is shown inFigure 2 and register addressing
in Table III. They show the name, address and page loca-
tions for the LV8573A.
TABLE III. Register/Counter/RAM
Addressing for LV8573A
A0-4
RS
Description
(Note 1)
CONTROL REGISTERS
00
01
02
03
04
01
02
03
04
X
0
0
0
0
1
1
1
1
Main Status Register
N/A
N/A
Periodic Flag Register
Time Save Control Register
Real Time Mode Register
Output Mode Register
Interrupt Control Register 0
Interrupt Control Register 1
COUNTERS (CLOCK CALENDAR)
05
06
07
08
09
0A
0B
0C
0D
0E
X
X
X
X
X
X
X
X
X
X
1/100, 1/10 Seconds
Seconds
Minutes
Hours
Days of Month
Months
Years
RAM
D0, D1 bits only
Day of Week
(0–99)
(0–59)
(0–59)
(1–12, 0–23)
(1–28/29/30/31)
(1–12)
(0–99)
(1–7)
0F
10
11
12
X
X
X
X
N/A
N/A
N/A
N/A
TIME COMPARE RAM
13
14
15
16
17
18
X
X
X
X
X
X
Sec Compare RAM
Min Compare RAM
Hours Compare RAM
DOM Compare RAM
Months Compare RAM (1–12)
DOW Compare RAM
(0–59)
(0–59)
(1–12, 0–23)
(1–28/29/30/31)
(1–7)
TIME SAVE RAM
19
1A
1B
1C
1D
X
X
X
X
X
Seconds Time Save RAM
Minutes Time Save RAM
Hours Time Save RAM
Day of Month Time Save RAM
Months Time Save RAM
1E
1F
1
X
RAM
RAM/Test Mode Register
Note 1:
RSDRegister Select (Bit D6 of Main Status Register)
10
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