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參數資料
| 型號： | LXP710PE |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數： | 1/84頁 |
| 文件大?。?/td> | 1108K |
| 代理商： | LXP710PE |
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LXP710
HDSL Framer/Mapper for 1168 kbps Applications
Datasheet
General Description
The LXP710 is a complete HDSL framer/mapper that multiplexes and demultiplexes a framed
or unframed 2.048 Mbps E1 data stream onto two 1168 kbps HDSL lines. The LXP710 also
supports point-to-point and point-to-multipoint fractional E1 applications with 1, 2 or 3 HDSL
lines.
The LXP710 interfaces directly with the Level One SK70704/SK70707 1168 kbps HDSL data
pump and industry standard E1 Framers or Line Interface ICs. The framer/mapper is controlled
and monitored by an external microprocessor using an 8-bit Intel or Motorola compatible
parallel interface. The framer/mapper provides both programmable and 6ms interrupts
synchronized to the HDSL frame rate.
The LXP710 provides fully programmable mapping between the E1 and HDSL interfaces on
one or more loops. The LXP710 provides support for system performance monitoring with
internal CRC, FEBE and BPV error counters and the capability to inject these errors.
The framer/mapper automatically controls the synchronization between the HDSL loop timing
and the E1 payload timing using a digital PLL for E1 timing recovery and a transmitter stuffing
control circuit.
Product Features
I
Compliant with ETSI ETR-152
requirements
I
Interfaces with 1, 2 or 3 Level One HDSL
Data Pumps and industry standard E1
Framers or Line Interface ICs
I
8-bit, Intel or Motorola compatible parallel
processor interface with programmable and
6ms interrupts
I
User definable 10 kbps overhead channel
I
HDSL Overhead Management
I
DPLL for E1 Timing Recovery
I
HDSL Transmit Stuffing Control
I
E1 to HDSL Loop Multiplexing/
Demultiplexing
—Programmable time slot mapping
—Accepts framed or unframed E1 data
—IDLE Code Insertion provides channel
blocking in mux and demux directions
—DS0 Channel Grouping
—Loopbacks toward E1 and HDSL
interfaces
I
Diagnostics/Performance Monitoring
—QRSS Pattern Generation and Detection
—CRC, BPV and FEBE counters and error
generators
As of January 15, 2001, this document replaces the Level One document
known as
HDSL Framer/Mapper for 1168 kbps Applications
.
Order Number:
249004-001
January 2001
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