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參數(shù)資料
| 型號(hào)： | M. CORE |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 57K |
| 代理商： | M. CORE |
This document can be
ordered by:
MCORE1/D
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Architectural Brief
MCORE
microRISC Engine
MCORE1
1997 Motorola, Inc. All Rights Reserved.
Semiconductor Products Sector
SEMICONDUCTOR PRODUCT INFORMATION
The 32-bit MCORE microRISC Engine represents a new line of Motorola microprocessor core products. The
processor architecture has been designed for high-performance and cost-sensitive embedded control
applications, with particular emphasis on reduced system power (energy) consumption, making it suitable for a
number of battery-operated, portable and mobile products.
Total system power consumption is dictated by various components in addition to the processor core. In
particular, memory power consumption (both on-chip and external) is expected to dominate overall power
consumption of the core+memory subsystem. With this factor in mind, the Instruction Set Architecture (ISA) for
MCORE makes the trade-off of absolute performance capability versus total energy consumption in favor of
reducing the overall energy consumption. This is accomplished, while maintaining an acceptably high level of
performance at a given clock frequency.
By designing a streamlined execution engine, many of the same performance enhancements and
implementation techniques used by desktop RISC designs are possible. By utilizing fixed-length instruction
encoding and defining a strict load/store architecture, control complexity and overhead is minimized. The goal
of minimizing the overhead memory system energy consumption is achieved by adopting a (relatively) short 16-
bit instruction encoding. This choice significantly lowers the memory bandwidth needed to sustain a high rate
of instruction execution. This careful selection of the instruction set for MCORE, allows the code density and
overall memory footprint (efficiency) of the MCORE architecture to approach and surpasses the code density
offered by traditional CISC architectures.
In addition to substantial cost and performance benefits, MCORE also offers advantages in power consumption
and power management. MCORE minimizes power dissipation by using a fully-static design, dynamic clock
management, and low-voltage operation. It automatically powers-down internal function blocks that are not
needed on a clock-by-clock basis. Power conservation modes, which are invoked via three low-power mode
instructions, provide for absolute lowest power consumption.
The primary features of the MCORE processor include the following:
32-bit Load/Store RISC Architecture
Fixed 16-bit Instruction Length
16 Entry 32-bit General Purpose Register File
Efficient 4-Stage Execution Pipeline, Hidden from Application Software
Single-Cycle Instruction Execution for most Instructions, Two cycles for Branches and Memory Access
Instructions
Support for Byte/Halfword/Word Memory Access
Fast Interrupt Support with 16-Entry User-Controlled Alternate Register File
Vectored and Autovectored Interrupt Support
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