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參數(shù)資料
| 型號(hào)： | M-CAS-C8237 |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE DMA CONTROLLER ALTERA CORE |
| 中文描述： | 可編程DMA控制器ALTERA公司的核心 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 404K |
| 代理商： | M-CAS-C8237 |
C8237
Programmable
DMA Controller
Altera Core
The C8237 Programmable DMA Controller core (C8237 core) is a peripheral inter-
face circuit for microprocessor systems. The core is designed for use with an
external, 8-bit address latch. It contains four independent channels and may be ex-
panded to any number or channels by cascading additional controller chips. Each
channel has a full 64K address and word count capability.
Applications
The C8237 core is designed to improve system performance by allowing external
devices to directly transfer information from the system memory.
Block Diagram
Enable/Disable control of indi-
vidual DMA requests
Four, independent DMA chan-
nels
Independent auto-initialization of
all channels
Memory-to-Memory transfers
Memory block initialization
Address increment of decrement
Directly expandable to any
number of channels
End of process input for termi-
nating transfers
Software DMA requests
Independent polarity control for
DREQ and DACK signals
The C8237 was developed in
HDL and synthesizes to ap-
proximately 5,500 gates
depending on the technology
used.
Functionality based on the Intel
8237
RESET
Timing
and
Control
CLK
CSN
AEN
READY
State
Machine
HLDA
16 Bit
Decrementor
Temp Word
Count Reg
16 Bit
Incrementor/
Decrementor
Temp Address Reg
C8237REG
Fixed
Priority
and
Rotating
Priority
Logic
DREQ(3:0)
HRQ
DACK(3:0)
Command
Register
Mask
Register
Request
Register
Mode
Register
Status
Register
Temporary
Register
DBIN(7:0)
AIN[3:0]
AOUT[7:0]
EOPNOUT
MEMRN
ADSTB
MEMWN
IOWNOUT
IORNOUT
IORNIN
IOWNIN
EOPNIN
DBOUT(7:0)
Channel-0
Current Word
Count Register
Current Word
Address Register
Base Word Count
Register
Base Word Address
Register
Write
Read/Write
Channel-1
Channel-2
Channel-3
March 2004
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