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參數資料
| 型號： | M-ORT82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數： | 1/94頁 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G51BM680-DB |
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www.latticesemi.com
1
ort82g5_01
ORCA
ORT82G5
1.0-3.7 Gbits/s
8b/10b Backplane Interface FPSC
October 2002
Preliminary Data Sheet
Introduction
Lattice Semiconductor has developed a next generation FPSC intended for high-speed serial backplane data
transmission. Built on the Series 4 recongurable embedded System-on-a-Chip (SoC) architecture, the ORT82G5
is made up of backplane transceivers containing eight channels, each operating at up to 3.7 Gbits/s (2.96 Gbits/s
data rate), with a full-duplex synchronous interface with built-in Rx Clock and Data Recovery (CDR), and transmit-
ter preemphasis along with more than 400K usable FPGA system gates. The CDR circuitry is a macrocell available
from Lattice’s smart silicon macro library and has already been implemented in numerous applications, including
ASICs, standard products, and FPSCs, to create interfaces for SONET/SDH, Fibre Channel, and Ethernet (GbE,
10 GbE) applications. With the addition of protocol and access logic such as protocol-independent framers, Fibre
Channel link layer capabilities, and framers for HDLC for Internet Protocol (IP), designers can build a congurable
interface retaining proven backplane driver/receiver technology.
Designers can also use the device to drive high-speed data transfer across buses within any generic system. For
example, designers can build a 20 Gbits/s bridge for 10 G Ethernet; the high-speed SERDES interfaces can com-
prise two XAUI interfaces with congurable back-end interfaces such as XGMII. The ORT82G5 can also be used to
provide a full 10 G backplane data connection with protection between a line card and switch fabric.
The ORT82G5 provides a clockless high-speed interface for interdevice communication on a board or across a
backplane. The built-in clock recovery of the ORT82G5 allows for higher system performance, easier-to-design
clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benet from the
backplane transceiver as a network termination device. The device supports embedded 8b/10b encoding/decoding
and link state machines for 10 G Ethernet, and Fibre Channel.
The ORT82G5 is pinout compatible with a sister device, the ORSO82G5, which implements 8 channels of SER-
DES with SONET scrambling and cell processing.
Table 1. ORCA ORT82G5 Family – Available FPGA Logic
Device
PFU Rows
PFU
Columns
Total PFUs
FPGA Max
User I/O
LUTs
EBR Blocks
EBR Bits
(K)
Usable
Gates (K)
1, 2
ORT82G5
36
1296
372
10,368
12
111
333 - 643
1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The System Gate ranges
are derived from the following: Minimum System Gates assumes 100% of the PFU's are used for logic only (No PFU RAM) with 40% EBR
usage and 2 PLL's. Maximum System Gates assumes 80% of the PFU's are for logic, 20% are used for PFU RAM, with 80% EBR usage and
6 PLL's."
2. There are two 4K X 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.
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