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參數資料
| 型號： | M100LVEP111FATWG |
| 廠商： | ON Semiconductor |
| 文件頁數： | 1/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:10 32-LQFP |
| 標準包裝： | 2,000 |
| 系列： | 100LVEP |
| 類型： | 扇出緩沖器（分配），多路復用器 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | ECL，HSTL，PECL |
| 輸出： | ECL，PECL |
| 頻率 - 最大： | 3GHz |
| 電源電壓： | 2.375 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應商設備封裝： | 32-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2012
October, 2012 Rev. 20
1
Publication Order Number:
MC100LVEP111/D
MC100LVEP111
2.5V / 3.3V 1:10 Differential
ECL/PECL/HSTL Clock Driver
Description
The MC100LVEP111 is a low skew 1to10 differential driver,
designed with clock distribution in mind, accepting two clock sources into
an input multiplexer. The PECL input signals can be either differential or
singleended (if the VBB output is used). HSTL inputs can be used when
the LVEP111 is operating under PECL conditions.
The LVEP111 specifically guarantees low outputtooutput skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
To ensure tightest skew, both sides of differential outputs identically
terminate into 50
W even if only one output is being used. If an output
pair is unused, both outputs may be left open (unterminated) without
affecting skew.
The MC100LVEP111, as with most other ECL devices, can be
operated from a positive VCC supply in PECL mode. This allows the
LVEP111 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Singleended CLK input operation is limited to a VCC ≥
3.0 V in PECL mode, or VEE v 3.0 V in NECL mode when using VBB
(See Figure 11). Full operating range is available when using an external
voltage reference (See Figure 10). Designers can take advantage of the
LVEP111’s performance to distribute low skew clocks across the
backplane or the board.
Features
85 ps Typical DevicetoDevice Skew
20 ps Typical OutputtoOutput Skew
Jitter Less than 1 ps RMS
Maximum Frequency > 3 GHz Typical
VBB Output
430 ps Typical Propagation Delay
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 2.375 V to 3.8 V
Open Input Default State
LVDS Input Compatible
Fully Compatible with MC100EP111
PbFree Packages are Available
32
1
LQFP32
FA SUFFIX
CASE 873A
MARKING
DIAGRAMS*
MC100
AWLYYWWG
LVEP111
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G or G = PbFree Package
QFN32
MN SUFFIX
CASE 488AM
32
1
MC100
LVEP111
AWLYYWW
G
1
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